Xilinx Virtex-5 FPGA ML550 User Manual

Also see for Virtex-5 FPGA ML561: User guide User guide User guide User guide User guide

Contents

30 www.xilinx.com ML550 Networking Interfaces PlatformUG202 (v1.4) April 18, 2008Chapter 3: Hardware Description R• Jumper OFF = Enabled• Jumper ON = InhibitedThe TI PTH05000 regulator module requires a fixed 5V input. The output is adjustable overa range of 0.9V to 3.6V by changing the resistor tied between pin 4 and GND.Table 3-10 shows the VR_SEL[3:0] settings used to control the voltage regulator outputs.Table 3-11 lists the pin locations for VR_SEL[3:0].Table 3-9: Voltage Regulators VR1 through VR5Regulator InhibitJumperTest PointConnectorMargin ControlStrobesVOUT Target Voltage (V)(1)–10% –7.5% –5% –2.5% Nom +2.5% +5% +7.5% +10%VR1System 3.3VP4 P1 STB_SYS3V3(FPGA U9:AD4)2.97 3.05 3.14 3.22 3.30 3.383 3.465 3.548 3.63VR2V CCINT 1.0VP14 P13 STB_VCCINT1V0(FPGA U9:AA6)0.90 0.93 0.95 0.98 1.00 1.025 1.05 1.075 1.1VR3System 2.5VP21 P16 STB_SYS2V5(FPGA U9:AD6)2.25 2.31 2.38 2.44 2.50 2.563 2.625 2.688 2.75VR4V CCO 2.5VP30 P22 STB_VCCO2V5(FPGA U9:Y7)2.25 2.31 2.38 2.44 2.50 2.563 2.625 2.688 2.75VR5VCCAUX 2.5VP38 P33 STB_VCCAUX2V5(FPGA U9:AD5)2.25 2.31 2.38 2.44 2.50 2.563 2.625 2.688 2.75Notes:1. ±5% margin limit.Table 3-10: Voltage Regulator Output Select VR_SELVR_SEL[3:0] VOUTSelected(1)3 2 1 00 0 0 1 –10%0 0 1 1 –7.5%0 1 0 1 –5%0 1 1 1 –2.5%- - - 0 Nominal1 0 0 1 +2.5%1 0 1 1 +5%1 1 0 1 +7.5%1 1 1 1 +10%Notes:1. ±5% margin limit.2. At power-on, FPGA_RESETB (FPGA U9.W34) is not driven and is pulled down by a 4.7 KΩ resistor.3. At power-on, V REG defaults to the nominal output.4. To enable margin control, the U9.W34 FPGA_RESETB pin must be driven High.5. To select other than the nominal output, set up the margin % on VR_SEL[3:0], then strobe theappropriate STB_* from Low to High to Low to clock the value into the latch.