Xilinx Virtex-5 FPGA ML550 User Manual Manual pdf 64 page image
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Xilinx Virtex-5 FPGA ML550 User Manual

Also see for Virtex-5 FPGA ML561: User guideUser guideUser guideUser guideUser guide

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Contents
  1. revision history
  2. Table Of Contents
  3. Table Of Contents
  4. Guide Contents
  5. Additional Support Resources
  6. Typographical Conventions
  7. About the Virtex-5 FPGA Source-Synchronous Interfaces Tool Kit
  8. Virtex-5 FPGA ML550 Networking Interfaces Development Board
  9. Documentation and Reference Design CD-ROM
  10. Installation
  11. BERT GUI Tcl Interface Installation
  12. Programmable Clock Module Switch Position Chart
  13. hardware description
  14. Clock Generation
  15. SDRAM Memory
  16. Liquid Crystal Display
  17. Display Hardware Design
  18. Hardware Schematic Diagrams
  19. User LED
  20. Configuration INIT and DONE LEDs
  21. Program Switch
  22. LVDS Connectors
  23. LVDS Loopback Board (Xilinx P/N 0431395)
  24. Important Note About ± 5% Margin Limits
  25. Power Monitor Connector
  26. ML550 System Monitor and Power Monitor Support
  27. ML550 Board System Monitor Support Circuitry Details
  28. V System Power Voltage Monitor
  29. V Input Power Current Monitor
  30. J19 Mezzanine Board Connector
  31. Power Monitor Circuitry
  32. Power Monitor Board
  33. Configuration Modes
  34. JTAG Chain
  35. JTAG Ports
  36. mm Flat Cable Port
  37. System ACE Interface
  38. LVDS Transmit Connectors
  39. LVDS Receive Connectors
  40. Appendix B: LVDS Loopback Board
  41. General
  42. Hardware Schematic Diagram
  43. Peripheral Device KS0713
  44. Controller – Operation
  45. Controller – LCD Panel Connections
  46. Controller – Power Supply Circuits
  47. Operation Example of the 64128EFCBC-3LP
  48. Instruction Set
  49. Read/Write Characteristics (6800 Mode)
  50. Design Examples
  51. LCD Panel Used in Character Mode
  52. Array Connector Numbering
Xilinx Virtex-5 FPGA ML550 User Manual Manual pdf 64 page image
64 www.xilinx.com ML550 Networking Interfaces PlatformUG202 (v1.4) April 18, 2008Appendix C: LCD Interface RTable C-1 summarizes the controller specifications.The on-chip RAM size is 65x132 = 8580 bits.Hardware Schematic DiagramTable C-1: Display Controller SpecificationsParameter SpecificationSupply voltage 2.4V to 3.6V (VDD )LCD driving voltage 4V to 15V (V LCD = V0 - V DD )Power consumption 70μA typical (V DD = 3V, x4 boost, V0 = 11V,internal supply = ON)Sleep mode 2μAStandby mode 10μAFigure C-1: Display Schematic Diagram3.3VLCD_D[7:0]ENA, R/W, RSEL, CS1BLCD-BUSDIP1_43.3VRst GndVcc- +LEDMI3.3V3.3V68xx68xxDefault = 68xxDefault =Resistor to GndBacklight ON/OFFIC19IC22IC23SamArrayUG202_C_01_050906
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Virtex-5 FPGA ML561
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