Xilinx Virtex-5 FPGA ML550 User Manual

Also see for Virtex-5 FPGA ML561: User guide User guide User guide User guide User guide

Contents

42 www.xilinx.com ML550 Networking Interfaces PlatformUG202 (v1.4) April 18, 2008Chapter 3: Hardware Description RFigure 3-21 shows a schematic diagram of the P72 pinouts. Refer to Table 3-16.Table 3-15: J19 Mezzanine Board ConnectorPin # Signal Name FPGA Pin # Schematic Notes1 VP_SM U18 30 Via 100Ω series resistor R4532 TD_P W18 30 FPGA internal temp diode DXP3 VN_SM V17 30 Via 100Ω series resistor R4524 TD_N W17 30 FPGA internal temp diode DXN5 Agnd 306 Agnd 307 REF_2V5_OUT U10.2 19, 30 U10 = REF3025 Voltage Reference8 SM_AVDD U9.T18,P39.2 19,30 P39 = 3-pin header (2.5V select)9 Agnd 3010 VCC5 21, 3011 VCC2V5 22, 3012 Dgnd 3013 Dgnd 3014 SM_GPIO1 N34 30, 3415 SM_GPIO2 P34 30, 3416 SM_GPIO3 M32 30, 3417 SM_GPIO4 L33 30, 34Figure 3-21: P72 Pinout Diagram (Sheet 20)135VCC57911131517192123252D468101214161820222426VCC1V0_VINT_S– 23,R386.324,R384.322,R385.322,R383.324,R387.319,R131.2(5V Current Monitor)19,R201.3VCC1V0_VINT_S+23,R386.223,R189.224,R384.224,R220.222,R385.222,R187.222,R383.222,R163.224,R387.224,R222.219,R201.2VCC1V0_VINT_MONVCC5_S+VCC3V3_SYS_S+VCC3V3_SYS_MONVCC2V5_MONVCC2V5_S+VCC2V5_VCCO_S+VCC2V5_VCCO_MONVCC2V5_VAUX_MONVCC2V5_VAUX_S+VCC2V5_VCCO_S–VCC3V3_SYS_S–VCC5_MONVCC5_S–VCC2V5_S–VCC2V5_VAUX_S–HDR_PROTECT 13x2 UG202_3_22_041508