Xilinx Virtex-5 FPGA ML550 User Manual

Also see for Virtex-5 FPGA ML561: User guide User guide User guide User guide User guide

Contents

74 www.xilinx.com ML550 Networking Interfaces PlatformUG202 (v1.4) April 18, 2008Appendix C: LCD Interface R• Normal power mode is set• The voltage follower and voltage regulator are set to:♦ Five times boost mode♦ The V4, V3, V2, V1, and V0 outputs depend on the bias settings of 1/9 or 1/7.Because of these default settings, the following display controller connections are not used:• DISP: Turns into an output when Master mode is selected• FRS: Static driver segment output• M: Used in Master/Slave display configurations• CL: Clock pin used in Master/Slave display configurationsWhen RESETB is Low, the display controller is initialized as indicated in Table C-4.When RESETB is High, the display must be initialized. The first steps to be taken toguarantee correct operation of the display and the controller are:• Configure the ADC bit. This bit determines the scanning direction of the segments.♦ When the RESETB signal is active, ADC is reset to 0, meaning that the segmentsare scanned from SEG1 up to SEG132.♦ When ADC is set to 1, the segments are scanned in opposite direction.• Configure the SHL bit. This bit sets the scanning direction of the COM lines.♦ When the RESETB signal is active, SHL is reset to 0, meaning that the segmentsare scanned from COM1 up to COM64.Table C-4: Display Controller Initialization (RESETB is Low)Parameter Initial ValueDisplay OFFEntire display OFFADC select OFFReverse display OFFPower control 0,0,0 (VC, VR, VF)LCD bias 1/7Read-modify-write OFFSHL select OFFStatic indicator mode OFFStatic indicator register 0,0 (S1, S0)Display start 0 (First line)Column address 0Page address 0Regulator select 0,0,0 (R2, R1, R0)Reference voltage OFFReference Voltage register 1,0,0,0,0,0 (SV5, SV4, SV3, SV2, SV1, SV0)