Xilinx Virtex-5 FPGA ML550 User Manual
Also see for Virtex-5 FPGA ML561: User guideUser guideUser guideUser guideUser guide
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32 www.xilinx.com ML550 Networking Interfaces PlatformUG202 (v1.4) April 18, 2008Chapter 3: Hardware Description RTo activate the margin control circuitry FPGA_RESETB is driven High, the desired marginresistor select data is setup on the VR_SEL[3:0] bus, and the data latch of the voltageregulator of interest is strobed to capture the resistor select data. See Margin ControlStrobes in Table 3-9. The latch output drives the analog mux switch select lines to causeselection of the appropriate RADJ resistor, which causes the regulator to adjust its output tothe selected margin voltage value.Each regulator has a two-pin test point connector associated with it (pin 1 = V OUT and pin2 = GND). To apply VOUT values other than the fixed set the voltage regulator can supply,first disable the on-board voltage regulator using the inhibit jumper shown in Figure 3-8,and then connect a bench-top power supply to the two-pin test point connector for thatvoltage. This provides bench-top power to the power plane and also “back powers” theoutput pin of the inhibited voltage regulator.Note: Do not turn OFF the 5V power to the ML550 Development Board while a bench-top powersupply is ON and attached to the board in the manner described above. The voltage regulator can bedamaged if the output is reverse powered and the 5V input is removed. Always turn the bench-toppower supply OFF first, then turn the 5V power to the ML550 Development Board OFF.Power Monitor ConnectorNot shown in Figure 3-8 or Figure 3-9 is the voltage plane current measurement resistor.Each voltage regulator is routed to its own 10 mΩ 1% 3W Kelvin current sense resistor. TheFigure 3-9: Margin Control Circuit Detailsug202_3_11_031406654123VADJVCCINV CCGNDCOMNDNCMAX4625RNom = 84.5 KΩU51 2R3684.5K1 2R334.7KU26MAX4781EUE12345678D1 2R7668.1K1 2R2756.2K1 2R2847.5K1 2R3841.2KX4X6XX7X5EN_8NCGND1 2R672.2M1 2R68348K1 2R70174K1 2R73115KDDVCC161514131211910VCCX2X1X0X3ABCVCCU25V CC1Q2Q3Q4Q4Q3Q2Q1QSN74LV175ADGND16271015361114845121391VR_SEL0VR_SEL2VR_SEL3VR_SEL1STB_VCCINT1V0FPGA_RESETB-10% +10%-7.5% +7.5%-5% +5%-2.5% +2.5%R NOM2:1 Mux8:1 MuxMargin ControlData Latch1D2D3D4DCLKCLR |
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