Xilinx Virtex-5 FPGA ML550 User Manual

Also see for Virtex-5 FPGA ML561: User guide User guide User guide User guide User guide

Contents

ML550 Networking Interfaces Platform www.xilinx.com 73UG202 (v1.4) April 18, 2008Hardware Schematic DiagramRThe voltage and contrast settings must be configured before the LCD panel is ready foroperation. Figure C-6 shows the initialization procedure required to set up the LCDcontroller.Operation Example of the 64128EFCBC-3LPThe KS0713 LCD controller has several default settings of operation on the LCD paneldisplay PCB. Some settings are forced through direct bonding on the chip. The defaultsettings are:• Master mode• Parallel mode• Internal oscillator• Duty cycle ratio is set to 1/65• Voltage converter input is between 2.4V ≤VDD ≤3.6V, where VDD connects to 3.3V• Internal voltage divider resistors• Temperature coefficient is set to -0.05%/° CFigure C-6: LCD Controller Initialization FlowEnd InitializationRegulator Resistor SelectSet Reference VoltageFPGA Configured and Application RunningRESETB Pin is Taken HIGHStart FPGA ConfigurationRESETB Pin is Kept LOWRESETB Pin is Kept LOWSetup Instruction FlowWait between each instruction longerthan 1 ms to let the voltages stabilize.The on-chip resistors are used.Therefore, the selection MUST beset to 101.Setting Reference Voltageis a two-pass instruction:- Set Reference Voltage Mode- Set Reference Voltage RegisterLCD BiasDUTY0, 1 is "11".LCD Bias 0 = 1/7LCD Bias 1 = 1/9SHL Select- SHL = 0 COM1 --> COM64- SHL = 1 COM64 --> COM1ADC Select- ADC = 0 SEG1 --> SEG132- ADC = 1 SEG132 --> SEG1Board Power Supply StartPower ONVoltage Converter ONVoltage Regulator ONVoltage Follower ONADC SelectSHL SelectLCD Bias SelectUG202_C_06_050906