Xilinx Virtex-5 FPGA ML550 User Manual

Also see for Virtex-5 FPGA ML561: User guide User guide User guide User guide User guide

Contents

ML550 Networking Interfaces Platform www.xilinx.com 83UG202 (v1.4) April 18, 2008Hardware Schematic DiagramRWhen presenting byte value 30 hex, character 0 must be displayed. Shifting the value00110000b (30h) up three positions gives the value 180h or 348d.Because each character uses eight byte locations, character 0 in the character set starts frommemory location 348 decimal.For example, character X has byte value 58h or 01011000b. Shifting this value threepositions gives the value 2C0h or 704d.Figure C-11 shows a block diagram of the LCD character generator controller. Characterdata is latched and then shifted left three positions. This shifted value is the start byte for acounter that outputs an address to the block RAM. The result is a stream of bytesrepresenting a character for the display.A small second counter determines when a new character is loaded into the block RAMaddress counter.Figure C-10: Block RAM OrganizationF0 - FFThe RAM array is divided inpages of eight bytes by 16,forming an array of 128 bytes.This array represents onecolumn of standard ASCII table.A character is stored as:E0 - EFD0 - DFC0 - CFB0 - BFA0 - AFNot UsedNot Used70 - 7F60 - 6F50 - 5F40 - 4F30 - 3F20 - 2F10 - 1FNot Used20471280127910241023N-xNN-1 ShiftDirectionAddr00 1 2 3 4 5 6 7 Data2562550Addr[10:0]Data[7:0]RAMB16_S9UG202_C_10_050906