Xilinx Zynq-7000 Design Manual

Also see for Zynq-7000: Quick start guide Getting started guide User guide Application note User guide

Zynq-7000 PCB Design Guide www.xilinx.com 50UG933 (v1.8) November 7, 2014Chapter 4: SelectIO SignalingLVTTL and LVCMOS do not specify any canonical termination method. Series termination isnot recommended for bidirectional interfaces. Parallel termination and weak drivers,however, are both appropriate.LVDCI and HSLVDCI both implicitly use controlled-impedance driver termination.HSTL Class II specifies parallel termination at both transceivers. The termination voltage V TTis defined as half of the supply voltage V CCO. The designer can elect either not to usetermination at all or to use a different termination. It is up to the designer to verify throughsimulation and measurement that the signal integrity at the receiver is adequate.The JEDEC specifications for SSTL provide examples of both series termination and paralleltermination. The termination voltage V TT is defined as half of the supply voltage V CCO.While the specification document provides examples depicting series termination at thedrivers, it is important to note that the purpose of this is to attempt to match theimpedance of the driver with that of the transmission line. Because the Zynq-7000 AP SoCSSTL drivers target to have output impedances close to 40–50Ω, better signal integrity canbe achieved without any external source-series termination. When possible, it is a betterstarting point to consider the use of the 3-state DCI I/O standards (“T_DCI”), which provideinternal parallel termination resistors that are only present when the output buffer is in3-state. It is up to the designer to carefully choose the I/O standard(s) at the 7 series device,drive strengths, and on-die termination (ODT) options at the other device(s) in the interface(usually DRAM ICs) and termination topography though careful simulation andmeasurement. See UG471, 7 Series FPGAs SelectIO User Guide for more details on theavailable I/O standards and options.Bidirectional Multi-Point TopographiesIn more complex topographies, any transceiver in a multi-point bus can transmit to all othertransceivers. Usually these topographies can only run at very slow clock rates because theyonly support very slow signal rise times (10 ns to 50 ns). While useful in some situations, thedrawbacks usually outweigh the benefits. The constraints involved in designing thesetopographies with good signal integrity are beyond the scope of this document.SSTL15 DCISSTL18 CLASS IISSTL18 CLASS II DCIHSTL CLASS IIHSTL CLASS II DCITable 4-3: Example I/O Interface Types for Bidirectional Point-to-Point I/O TopographiesSend Feedback