Xilinx Zynq-7000 Design Manual

Also see for Zynq-7000: Quick start guide Getting started guide User guide Application note User guide

Zynq-7000 PCB Design Guide www.xilinx.com 57UG933 (v1.8) November 7, 2014Chapter 5: Processing System (PS) Power and SignalingDynamic MemoryZynq-7000 AP SoC devices support DDR2, DDR3/3L, and LPDDR2 (mobile DDR) dynamicmemory. The memory is connected to dedicated pins in I/O Bank 502. This bank hasdedicated I/O, termination, and reference voltage supplies.DDR runs at very high speeds and special care need to be taken in board layout to ensuresignal integrity. The following sections show the recommendations for DDR memorydesigns for Zynq-7000 AP SoC devices.DDR Interface Signal PinsTable 5-4 lists all dynamic memory interface signals in Bank 502.X-Ref Target - Figure 5-4Figure 5-4: Setting Mode PinsUG585_c30_03_020713GNDVCCO_MIO0123MIO20 KΩTable 5-4: DDR Interface Signal PinsPin Name Direction DescriptionDDR_CK_P O Differential clock output positiveDDR_CK_N O Differential clock output negativeDDR_CKE O Clock enableDDR_CS_B O Clock selectDDR_RAS_B O RAS row address selectDDR_CAS_B O CAS column address selectDDR_WE_B O Write enableDDR_BA[2:0] O Bank addressDDR_A[14:0] O AddressDDR_ODT O Output dynamic terminationDDR_DRST_B O ResetSend Feedback