Xilinx Zynq-7000 Design Manual

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Zynq-7000 PCB Design Guide www.xilinx.com 64UG933 (v1.8) November 7, 2014Chapter 5: Processing System (PS) Power and SignalingNote: For PS_DDR_DQxx, ensure that byte lines are kept together. PS_DDR_ADDR0 should always beused. If bits must be omitted for chip select or other functionality, omit upper bit (PS_ADDR14)instead.In a balanced T-branch configuration, trace lengths TL1, TL2 and Tsub shall be kept as shortas possible; Rterm shall be close to and balanced among the loads.In a point-to-point configuration, Rterm shall be placed behind and close to the last load.In the fly-by topology, TL0 should be kept from 0-64 mm, with TL1 14 mm ±0.1 mm, andTL2 from 6-20 mm.Table 5-12 shows the recommended routing topologies. Byte and bit swapping is allowedto facilitate PCB routing, except for LPDDR2, which specifically forbids swapping. Whenswapping bits, keep all bits within the same byte group.X-Ref Target - Figure 5-8Figure 5-8: DDR Routing TopologiesZYNQ DDRVTT VTTTsubTsubTL2TL0TL1Rterm RtermBalanced T-branchPoint-to-pointUG585_c30_07_091913DDRDDRDDRDDRDDR DDR DDR DDRVTTRtermTL0 TL1 TL1 TL1 TL2Fly-byTable 5-12: DDR Routing TopologySignal Group LPDDR2 DDR2 DDR3/3L Number of DDRDevicesData Point-to-point Point-to-point Point-to-pointClockPoint-to-point Point-to-point Point-to-point 1T-branch T-branch Fly-by 2N/A T-branch Fly-by 4Address,Command,ControlPoint-to-point Point-to-point Point-to-point 1T-branch T-branch Fly-by/T-branch 2N/A T-branch Fly-by/T-branch 4Send Feedback