Xilinx Zynq-7000 Design Manual

Also see for Zynq-7000: Quick start guide Getting started guide User guide Application note User guide

Zynq-7000 PCB Design Guide www.xilinx.com 61UG933 (v1.8) November 7, 2014Chapter 5: Processing System (PS) Power and SignalingDDR Supply VoltagesTable 5-6 lists the different supply, reference and termination voltages required forLPDDR2/DDR2/DDR3 memory. These voltages are also required to power the DDR I/O bank,reference, and termination voltages.Note: VREF should track the midpoint of the VDD supplied to the DRAM and ground vialow-impedance paths. This can be done with a resistive divider or by a regulator that tracks thismidpoint. If resistive dividers are used, a separate divider and high-frequency decoupling capacitoris recommended for each IC. If a regulator is used, a low impedance plane or planelet isrecommended for distribution.X-Ref Target - Figure 5-7Figure 5-7: LPDDR2 Board ImplementationVREF VDDQVREF VDDQVREF VDDQVREF VDDQVDDQRdownVREF VDDQVREF VDDQAddr, Command, Contrl(Addr, cs_b)Addr, Command, Contrl(CA, cs_b)clkckeclkckeAddr, Command, Contrl(CA, cs_b)clkCkeVRNVRPData Group 0(dq, dqs, dm)Data Group 1(dq, dqs, dm)Data Group 2(dq, dqs, dm)Data Group 0(dq, dqs, dm)Data Group 1(dq, dqs, dm)Data Group 0(dq, dqs, dm)Data Group 1(dq, dqs, dm)UG933_c5_06_102413Data Group 3(dq, dqs, dm)RvrnpRvrnpzqRzqzqRzqZYNQLPDDR2LPDDR2Table 5-6: DDR VoltageVoltage LPDDR2 DDR2 DDR3 DDR3L CommentsV CCO_DDRV DDQ1.2V 1.8V 1.5V 1.35V LPDDR2 devices also require V DD1 (1.8V) andV DD2 (1.2V)Send Feedback