Xilinx Zynq-7000 Design Manual

Also see for Zynq-7000: Quick start guide Getting started guide User guide Application note User guide

Zynq-7000 PCB Design Guide www.xilinx.com 66UG933 (v1.8) November 7, 2014Chapter 5: Processing System (PS) Power and Signalingthe Zynq-7000 AP SoC device and SD chip. PCB and package delay skew for SD_DAT[0:3]and SD_CMD relative to SD_CLK should be less than ±50 ps. Asynchronous signals SD_CDnand SD_WPn have no timing relationship to SD_CLK.The Cdn and WPn lines should both be pulled up with their own 50 kΩ resistors to the MIOI/O voltage.RECOMMENDED: It is highly recommended to perform a signal integrity analysis on the CLK line at thenear (close to Zynq-7000 AP SoC device) and far ends.Temperature Sensing DiodesNote: If unused, the DXP and DXN pins for the temperature sensing interface should be tiedto ground.Trace Port Interface Unit (TPIU)When operating the TPIU in MIO mode, the trace clock output should be delayed byapproximately one half clock period. This can be done on the PCB, or by the debuggingdevice (ARM_DSTREAM, Lauterbach, Agilent, etc).UARTFor MIO pins 14 and 15, keep trace delays below 1.75 nS. Match TX line to +/-50 pS, and RXline to +/-50 pS.Trace BTx Path: The clock to data skew should be targeted to 2.6 ns to center align the clock to thedata for all voltages. This shift must be provided either on the board or by the tracedebugger tools. ARM DSTREAM, Lauterbach & Agilent Trace debugger tools supportindividually adjustable trace clk/data signals.USB ULPIPCB and package delay should be kept to 2.0 ns or shorter to meet the 60 MHz operatingtarget. PCB and package delay skew for DATA[7:0], DIR, NXT, and STP should be less than±100 ps.RECOMMENDED: It is recommended that the clock trace should always be shorter than the data andcontrol signals to improve hold time.Send Feedback