Xilinx Zynq-7000 Design Manual

Also see for Zynq-7000: Quick start guide Getting started guide User guide Application note User guide

Zynq-7000 PCB Design Guide www.xilinx.com 9UG933 (v1.8) November 7, 2014Chapter 2: PCB Technology BasicsLandsFor the purposes of soldering surface mount components, pads on outer layers are typicallyreferred to as lands or solder lands. Making electrical connections to these lands usuallyrequires vias. Due to manufacturing constraints of PTH technology, it is rarely possible toplace a via inside the area of the land. Instead, this technology uses a short section of traceconnecting to a surface pad. The minimum length of the connecting trace is determined byminimum dimension specifications from the PCB manufacturer. Microvia technology is notconstrained, and vias can be placed directly in the area of a solder land.DimensionsThe major factors defining the dimensions of the PCB are PCB manufacturing limits, AP SoCpackage geometries, and system compliance. Other factors such as Design ForManufacturing (DFM) and reliability impose further limits, but because these areapplication specific, they are not documented in this user guide.The dimensions of the AP SoC package, in combination with PCB manufacturing limits,define most of the geometric aspects of the PCB structures described in this section, bothdirectly and indirectly. This significantly constrains the PCB designer. The package ball pitch(1.0 mm for FF packages) defines the land pad layout. The minimum surface feature sizes ofcurrent PCB technology define the via arrangement in the area under the device. Minimumvia diameters and keep-out areas around those vias are defined by the PCB manufacturer.These diameters limit the amount of space available in-between vias for routing of signalsin and out of the via array underneath the device. These diameters define the maximumtrace width in these breakout traces. PCB manufacturing limits constrain the minimum tracewidth and minimum spacing.The total number of PCB layers necessary to accommodate an AP SoC is defined by thenumber of signal layers and the number of plane layers.• The number of signal layers is defined by the number of I/O signal traces routed in andout of an AP SoC package (usually following the total User I/O count of the package).• The number of plane layers is defined by the number of power and ground plane layersnecessary to bring power to the AP SoC and to provide references and isolation forsignal layers.Most PCBs for large AP SoCs range from 12 to 22 layers.System compliance often defines the total thickness of the board. Along with the number ofboard layers, this defines the maximum layer thickness, and therefore, the spacing in the Zdirection of signal and plane layers to other signal and plane layers. Z-direction spacing ofsignal trace layers to other signal trace layers affects crosstalk. Z-direction spacing of signaltrace layers to reference plane layers affects signal trace impedance. Z-direction spacing ofplane layers to other plane layers affects power system parasitic inductance.Send Feedback