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NXP Semiconductors MC9S08PA4 manuals

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MC9S08PA4

Brand: NXP Semiconductors | Category: Microcontrollers
Table of contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
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  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. Table Of Contents
  17. Table Of Contents
  18. Table Of Contents
  19. Table Of Contents
  20. Introduction
  21. MCU block diagram
  22. System clock distribution
  23. Device pin assignment
  24. Pin functions
  25. Oscillator (XTAL, EXTAL)
  26. External reset pin (RESET) and interrupt pin (IRQ)
  27. Background/mode select (BKGD/MS)
  28. Port A input/output (I/O) pins (PTA5–PTA0)
  29. Peripheral pinouts
  31. Wait mode
  32. Active BDM enabled in stop3 mode
  33. Low voltage detect (LVD) system
  34. Power-on reset (POR) operation
  35. Bandgap reference
  36. System Power Management Status and Control 2 Register (PMC_SPMSC2)
  37. Memory map
  38. Reset and interrupt vector assignments
  39. Register addresses and bit assignments
  40. Random-access memory (RAM)
  41. Flash and EEPROM
  42. Function descriptions
  43. Flash and EEPROM initialization after system reset
  44. Flash and EEPROM interrupts
  45. Protection
  46. Security
  47. Flash and EEPROM commands
  48. Flash and EEPROM command summary
  49. Flash and EEPROM registers descriptions
  50. Flash Security Register (NVM_FSEC)
  51. Flash CCOB Index Register (NVM_FCCOBIX)
  52. Flash Error Configuration Register (NVM_FERCNFG)
  53. Flash Status Register (NVM_FSTAT)
  54. Flash Error Status Register (NVM_FERSTAT)
  55. Flash Protection Register (NVM_FPROT)
  56. EEPROM Protection Register (NVM_EEPROT)
  57. Flash Common Command Object Register:High (NVM_FCCOBHI)
  58. Flash Common Command Object Register: Low (NVM_FCCOBLO)
  59. Interrupts
  60. Interrupt stack frame
  61. Interrupt vectors, sources, and local masks
  62. Hardware nested interrupt
  63. Interrupt priority level register
  64. Interrupt priority level comparator set
  65. Integration and application of the IPC
  66. Features
  67. Pin configuration options
  68. Interrupt Pin Request Status and Control Register (IRQ_SC)
  69. Interrupt priority control register
  70. IPC Status and Control Register (IPC_SC)
  71. Interrupt Priority Mask Pseudo Stack Register (IPC_IPMPS)
  72. System device identification (SDID)
  73. System options
  74. FTM0 channels pin reassignment
  75. ACMP output selection
  76. SCI0 RxD filter
  77. ADC hardware trigger
  78. System Reset Status Register (SYS_SRS)
  79. System Background Debug Force Reset Register (SYS_SBDFR)
  80. System Device Identification Register: Low (SYS_SDIDL)
  81. System Options Register 2 (SYS_SOPT2)
  82. System Options Register 3 (SYS_SOPT3)
  83. Illegal Address Register: High (SYS_ILLAH)
  84. Universally Unique Identifier Register 1 (SYS_UUID1)
  85. Universally Unique Identifier Register 3 (SYS_UUID3)
  86. Universally Unique Identifier Register 5 (SYS_UUID5)
  87. Universally Unique Identifier Register 7 (SYS_UUID7)
  89. Port data and data direction
  90. Input glitch filter setting
  91. Port A Data Register (PORT_PTAD)
  92. Port B Data Register (PORT_PTBD)
  93. Port High Drive Enable Register (PORT_HDRVE)
  94. Port B Output Enable Register (PORT_PTBOE)
  95. Port C Output Enable Register (PORT_PTCOE)
  96. Port A Input Enable Register (PORT_PTAIE)
  97. Port B Input Enable Register (PORT_PTBIE)
  98. Port C Input Enable Register (PORT_PTCIE)
  99. Port Filter Register 0 (PORT_IOFLT0)
  100. Port Filter Register 2 (PORT_IOFLT2)
  101. Port Clock Division Register (PORT_FCLKDIV)
  102. Port A Pullup Enable Register (PORT_PTAPE)
  103. Port B Pullup Enable Register (PORT_PTBPE)
  104. Port C Pullup Enable Register (PORT_PTCPE)
  105. Clock module
  106. Internal clock source (ICS)
  107. Function description
  108. Bus frequency divider
  109. Fixed frequency clock (ICSFFCLK)
  110. BDC clock
  111. FLL engaged internal (FEI)
  112. FLL engaged external (FEE)
  113. FLL bypassed internal low power (FBILP)
  114. Stop (STOP)
  115. FLL lock and clock monitor
  116. Initializing FEI mode
  117. Initializing FBE mode
  118. Bypass mode
  119. High-gain configuration
  120. kHz low-power oscillator (LPO)
  121. ICS Control Register 1 (ICS_C1)
  122. ICS Control Register 2 (ICS_C2)
  123. ICS Control Register 3 (ICS_C3)
  124. ICS Status Register (ICS_S)
  125. OSC Status and Control Register (ICS_OSCSC)
  126. System clock gating control registers
  127. System Clock Gating Control 1 Register (SCG_C1)
  128. System Clock Gating Control 2 Register (SCG_C2)
  129. System Clock Gating Control 3 Register (SCG_C3)
  131. System modules
  132. Memory
  133. Timers
  134. FTM0 interconnection
  135. FTM1 interconnection
  136. Communication interfaces
  137. SCI0 infrared functions
  138. Analog
  139. ADC channel assignments
  140. Alternate clock
  141. Analog comparator (ACMP)
  142. ACMP configuration information
  143. Human-machine interfaces HMI
  145. Programmer's Model and CPU Registers
  146. Index Register (H:X)
  147. Program Counter (PC)
  148. Addressing Modes
  149. Inherent Addressing Mode (INH)
  150. Direct Addressing Mode (DIR)
  151. Indexed Addressing Mode
  152. Indexed, 8-Bit Offset with Post Increment (IX1+)
  153. SP-Relative, 16-Bit Offset (SP2)
  154. Indexed to Direct, Post Increment
  156. Security mode
  157. HCS08 V6 Opcodes
  158. Instruction Set Summary
  160. KBI in Wait mode
  161. External signals description
  162. KBI Status and Control Register (KBIx_SC)
  163. KBIx Edge Select Register (KBIx_ES)
  164. Edge-only sensitivity
  165. KBI initialization
  167. Modes of operation
  168. Signal description
  169. EXTCLK — FTM external clock
  170. Status and Control (FTMx_SC)
  171. Counter High (FTMx_CNTH)
  172. Counter Low (FTMx_CNTL)
  173. Modulo Low (FTMx_MODL)
  174. Channel Value High (FTMx_CnVH)
  175. Channel Value Low (FTMx_CnVL)
  176. Clock Source
  177. Prescaler
  178. Up-down counting
  179. Free running counter
  180. Output compare mode
  181. Edge-aligned PWM (EPWM) mode
  182. Center-aligned PWM (CPWM) mode
  183. Update of the registers with write buffers
  184. CnVH:L registers
  185. FTM Interrupts
  188. RTC Status and Control Register 1 (RTC_SC1)
  189. RTC Status and Control Register 2 (RTC_SC2)
  190. RTC Modulo Register: High (RTC_MODH)
  191. RTC Counter Register: Low (RTC_CNTL)
  192. RTC operation example
  194. Block diagram
  195. SCI signal descriptions
  196. SCI Baud Rate Register: High (SCIx_BDH)
  197. SCI Baud Rate Register: Low (SCIx_BDL)
  198. SCI Control Register 2 (SCIx_C2)
  199. SCI Status Register 1 (SCIx_S1)
  200. SCI Status Register 2 (SCIx_S2)
  201. SCI Control Register 3 (SCIx_C3)
  202. SCI Data Register (SCIx_D)
  203. Baud rate generation
  204. Send break and queued idle
  205. Receiver functional description
  206. Data sampling technique
  207. Receiver wake-up operation
  208. Interrupts and status flags
  209. Baud rate tolerance
  210. Slow data tolerance
  211. Fast data tolerance
  212. Additional SCI functions
  213. Loop mode
  216. Analog Channel Inputs (ADx)
  217. Status and Control Register 2 (ADC_SC2)
  218. Status and Control Register 3 (ADC_SC3)
  219. Status and Control Register 4 (ADC_SC4)
  220. Conversion Result High Register (ADC_RH)
  221. Conversion Result Low Register (ADC_RL)
  222. Compare Value High Register (ADC_CVH)
  223. Pin Control 1 Register (ADC_APCTL1)
  224. Functional description
  225. Clock select and divide control
  226. Hardware trigger
  227. Completing conversions
  228. Power control
  229. Automatic compare function
  230. FIFO operation
  231. MCU Stop3 mode operation
  232. Initialization information
  233. Pseudo-code example
  235. Application information
  236. Analog reference pins
  237. Sources of error
  238. Code width and quantization error
  239. Code jitter, non-monotonicity, and missing codes
  242. External signal description
  243. ACMP Control and Status Register (ACMP_CS)
  244. ACMP Control Register 0 (ACMP_C0)
  245. ACMP Control Register 2 (ACMP_C2)
  246. Setup and operation of ACMP
  247. Resets
  250. Memory map and register definition
  251. Watchdog Control and Status Register 2 (WDOG_CS2)
  252. Watchdog Counter Register: High (WDOG_CNTH)
  253. Watchdog Timeout Value Register: High (WDOG_TOVALH)
  254. Watchdog Window Register: High (WDOG_WINH)
  256. Window mode
  257. Example code: Refreshing the Watchdog
  258. Reconfiguring the Watchdog
  259. Using interrupts to delay resets
  260. Fast testing of the watchdog
  261. Entering user mode
  263. Background debug controller (BDC)
  264. BKGD pin description
  265. Communication details
  266. BDC commands
  267. BDC hardware breakpoint
  268. Comparators A and B
  269. Bus capture information and FIFO operation
  270. Change-of-flow information
  271. Trigger modes
  272. Hardware breakpoints
  273. Memory map and register description
  274. BDC Breakpoint Match Register: High (BDC_BKPTH)
  275. BDC Breakpoint Register: Low (BDC_BKPTL)
  279. Debug Comparator A High Register (DBG_CAH)
  280. Debug Comparator A Low Register (DBG_CAL)
  281. Debug Comparator B High Register (DBG_CBH)
  282. Debug Comparator C High Register (DBG_CCH)
  283. Debug Comparator C Low Register (DBG_CCL)
  284. Debug FIFO Low Register (DBG_FL)
  285. Debug Comparator A Extension Register (DBG_CAX)
  286. Debug Comparator B Extension Register (DBG_CBX)
  287. Debug Comparator C Extension Register (DBG_CCX)
  288. Debug FIFO Extended Information Register (DBG_FX)
  289. Debug Trigger Register (DBG_T)
  290. Debug Status Register (DBG_S)
  291. Debug Count Status Register (DBG_CNT)
  293. Breakpoints
  294. Trigger selection
  295. Begin- and end-trigger
  297. FIFO
  298. Storing data in FIFO
  299. Reading data from FIFO
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