15.4.4.2 Completing conversionsA conversion is completed when the result of the conversion is transferred into the dataresult registers, ADC_RH and ADC_RL. This is indicated by the setting ofADC_SC1[COCO]. An interrupt is generated if ADC_SC1[AIEN] is high at the time thatADC_SC1[COCO] is set.A blocking mechanism prevents a new result from overwriting previous data in ADC_RHand ADC_RL if the previous data is in the process of being read while in 12-bit or 10-bitMODE (the ADC_RH register has been read but the ADC_RL register has not). Whenblocking is active, the data transfer is blocked, ADC_SC1[COCO] is not set, and the newresult is lost. In the case of single conversions with the compare function enabled and thecompare condition false, blocking has no effect and ADC operation is terminated. In allother cases of operation, when a data transfer is blocked, another conversion is initiatedregardless of the state of ADC_SC1[ADCO] whether single or continuous conversionsare enabled.If single conversions are enabled, the blocking mechanism could result in severaldiscarded conversions and excess power consumption. To avoid this issue, the dataregisters must not be read after initiating a single conversion until the conversioncompletes.In fifo mode, a blocking mechanism will keep current channel conversion and no channelfifo and result fifo switching until a block mechanism is released.15.4.4.3 Aborting conversionsAny conversion in progress is aborted in the following cases:• A write to ADC_SC1 occurs.• The current conversion will be aborted and a new conversion will be initiated, ifADC_SC1[ADCH] are not all 1s and ADC_SC4[AFDEP] are all 0s.• The current conversion and the rest of conversions will be aborted and no newconversion will be initialed, if ADC_SC4[AFDEP] are not all 0s.• A new conversion will be initiated when the FIFO is re-fulfilled upon the levelsindicated by the ADC_SC4[AFDEP] bits).• A write to ADC_SC2, ADC_SC3, ADC_SC4, ADC_CVH, or ADC_CVL occurs.This indicates a mode of operation change has occurred and the current and rest ofconversions (when ADC_SC4[AFDEP] are not all 0s) are therefore invalid.• The MCU is reset.• The MCU enters Stop mode with ADACK not enabled.Functional descriptionMC9S08PA4 Reference Manual, Rev. 5, 08/2017310 NXP Semiconductors
