Table 4-5. Reserved flash memory addresses (continued)Address Register Name Bit 7 6 5 4 3 2 1 Bit 00xFF7E NV_FOPT NV0xFF7F NV_FSEC KEYEN 1 1 1 1 SECThe 8-byte comparison key can be used to temporarily disengage memory securityprovided the key enable field, NV_FSEC[KEYEN], is 10b. This key mechanism can beaccessed only through user code running in secure memory. A security key cannot beentered directly through background debug commands. This security key can be disabledcompletely by programming the NV_FSEC[KEYEN] bit to 0. If the security key isdisabled, the only way to disengage security is by mass erasing the flash if needed,normally through the background debug interface and verifying that flash is blank. Toavoid returning to secure mode after the next reset, program the security bits,NV_FSEC[SEC], to the unsecured state (10b).4.4 Random-access memory (RAM)This section describes the 512 bytes of RAM (random-access memory).These devices include static RAM. The locations in RAM below 0x0100 can be accessedusing the more efficient direct addressing mode. Any single bit in this area can beaccessed with the bit manipulation instructions (BCLR, BSET, BRCLR, and BRSET).The RAM retains data when the MCU is in low-power wait, or stop3 mode. At power-on,the contents of RAM are uninitialized. RAM data is unaffected by any reset provided thatthe supply voltage does not drop below the minimum value for RAM retention.For compatibility with older M68HC05 MCUs, the HCS08 resets the stack pointer to0x00FF. In this series, re-initialize the stack pointer to the top of the RAM so that thedirect-page RAM can be used for frequently accessed RAM variables and bit-addressableprogram variables. Include the following 2-instruction sequence in your resetinitialization routine (where RamLast is equated to the highest address of the RAM in theequate file).LDHX #RamLast+1 ;point one past RAMTXS ;SP<-(H:X-1)When security is enabled, the RAM is considered a secure memory resource and is notaccessible through BDM or code executing from non-secure memory.Chapter 4 Memory mapMC9S08PA4 Reference Manual, Rev. 5, 08/2017NXP Semiconductors 55
