Section number Title Page7.7.12 Port Filter Register 2 (PORT_IOFLT2)...........................................................................................................1447.7.13 Port Clock Division Register (PORT_FCLKDIV).......................................................................................... 1457.7.14 Port A Pullup Enable Register (PORT_PTAPE)............................................................................................. 1467.7.15 Port B Pullup Enable Register (PORT_PTBPE)..............................................................................................1477.7.16 Port C Pullup Enable Register (PORT_PTCPE)..............................................................................................148Chapter 8Clock management8.1 Clock module.................................................................................................................................................................. 1518.2 Internal clock source (ICS)............................................................................................................................................. 1528.2.1 Function description.........................................................................................................................................1538.2.1.1 Bus frequency divider...................................................................................................................... 1548.2.1.2 Low power bit usage........................................................................................................................ 1548.2.1.3 Internal reference clock (ICSIRCLK)..............................................................................................1548.2.1.4 Fixed frequency clock (ICSFFCLK)................................................................................................1558.2.1.5 BDC clock........................................................................................................................................1568.2.2 Modes of operation.......................................................................................................................................... 1568.2.2.1 FLL engaged internal (FEI)............................................................................................................. 1578.2.2.2 FLL engaged external (FEE)............................................................................................................1588.2.2.3 FLL bypassed internal (FBI)............................................................................................................1588.2.2.4 FLL bypassed internal low power (FBILP)..................................................................................... 1588.2.2.5 FLL bypassed external (FBE).......................................................................................................... 1598.2.2.6 FLL bypassed external low power (FBELP)................................................................................... 1598.2.2.7 Stop (STOP)..................................................................................................................................... 1608.2.3 FLL lock and clock monitor.............................................................................................................................1618.2.3.1 FLL clock lock................................................................................................................................. 1618.2.3.2 External reference clock monitor..................................................................................................... 1618.3 Initialization / application information........................................................................................................................... 1618.3.1 Initializing FEI mode....................................................................................................................................... 1628.3.2 Initializing FBI mode....................................................................................................................................... 162MC9S08PA4 Reference Manual, Rev. 5, 08/20178 NXP Semiconductors
