/* the following code segment demonstrates initializing external oscillator *//* supposing external 32768Hz crystal is installed in low power mode */ICS_OSCSC = 0xA0; /* low-range, low-power, oscillator required, ERCLK enabled in stop mode */while (ICS_OSCSC_OSCINIT == 0); /* waiting until oscillator is ready */8.4 1 kHz low-power oscillator (LPO)The 1 kHz low-power oscillator acts as a standalone low-frequency clock source in allrun, wait, and stop3 modes.8.5 Peripheral clock gatingThis device includes a clock gating system to manage the bus clock sources to theindividual peripherals. Using this system, the user can enable or disable the bus clock toeach of the peripherals at the clock source, eliminating unnecessary clocks to peripheralsthat are not in use, thereby reducing the overall run and wait mode currents.Out of reset, all peripheral clocks will be enabled. For lowest possible run wait currents,user software should disable the clock source to any peripheral not in use. The actualclock will be enabled or disabled immediately following the write to the Clock GatingControl registers (SCG_Cx). Any peripheral with a gated clock cannot be used unless itsclock is enabled. Writing to the registers of a peripheral with a disabled clock has noeffect.NoteUser software should disable the peripheral before disabling theclocks to the peripheral. When clocks are re-enabled to aperipheral, the peripheral registers need to be re-initialized byuser software.In stop modes, the bus clock is disabled for all gated peripherals, regardless of the settingin SCG_Cx registers.8.6 ICS control registers1 kHz low-power oscillator (LPO)MC9S08PA4 Reference Manual, Rev. 5, 08/2017166 NXP Semiconductors
