Section number Title Page6.6.9 Illegal Address Register: Low (SYS_ILLAL)................................................................................................. 1266.6.10 Universally Unique Identifier Register 1 (SYS_UUID1)................................................................................ 1276.6.11 Universally Unique Identifier Register 2 (SYS_UUID2)................................................................................ 1276.6.12 Universally Unique Identifier Register 3 (SYS_UUID3)................................................................................ 1286.6.13 Universally Unique Identifier Register 4 (SYS_UUID4)................................................................................ 1286.6.14 Universally Unique Identifier Register 5 (SYS_UUID5)................................................................................ 1296.6.15 Universally Unique Identifier Register 6 (SYS_UUID6)................................................................................ 1296.6.16 Universally Unique Identifier Register 7 (SYS_UUID7)................................................................................ 1306.6.17 Universally Unique Identifier Register 8 (SYS_UUID8)................................................................................ 130Chapter 7Parallel input/output7.1 Introduction.....................................................................................................................................................................1317.2 Port data and data direction.............................................................................................................................................1337.3 Internal pullup enable..................................................................................................................................................... 1337.4 Input glitch filter setting..................................................................................................................................................1347.5 High current drive........................................................................................................................................................... 1347.6 Pin behavior in stop mode...............................................................................................................................................1347.7 Port data registers............................................................................................................................................................1347.7.1 Port A Data Register (PORT_PTAD).............................................................................................................. 1357.7.2 Port B Data Register (PORT_PTBD).............................................................................................................. 1367.7.3 Port C Data Register (PORT_PTCD).............................................................................................................. 1367.7.4 Port High Drive Enable Register (PORT_HDRVE)........................................................................................1377.7.5 Port A Output Enable Register (PORT_PTAOE)............................................................................................1377.7.6 Port B Output Enable Register (PORT_PTBOE)............................................................................................ 1387.7.7 Port C Output Enable Register (PORT_PTCOE)............................................................................................ 1397.7.8 Port A Input Enable Register (PORT_PTAIE)................................................................................................ 1407.7.9 Port B Input Enable Register (PORT_PTBIE)................................................................................................ 1417.7.10 Port C Input Enable Register (PORT_PTCIE)................................................................................................ 1427.7.11 Port Filter Register 0 (PORT_IOFLT0)...........................................................................................................143MC9S08PA4 Reference Manual, Rev. 5, 08/2017NXP Semiconductors 7
