synchronous and asynchronous peripherals can be freely mixed on a cable connectedto the AHA-1740A/1742A/1744.In addition, the host adapter has the ability to select particular targets during con-figuration to initiate synchronous negotiation, enable parity checking, send start-up,and allow disconnection. The current limiting fuse on other host adapters has been re-placed with a thermistor to allow nondestructive current limiting of terminatorpower supplied to the SCSI cable.The AHA-1740A/1742A/1744 utilizes the Adaptec AIC-6251 Fast SCSI protocol chipto maximize the SCSI bus utilization. The AIC-6251 is an Adaptec VLSI developmentof the popular AIC-6250 device which allows the AHA-1740A/1742A/1744 to achievegreater than 2.0 MBytes/second asynchronous SCSI data transfer rates, and up to 10MBytes/second synchronous data transfer rates. The AIC-6251 will also enable theAHA-1740A/1742A/1744 to operate simultaneously as both an initiator and as a proc-essor target device.Through a 16-bit interface internal to the board, the AIC-6251 reduces bus busy timeduring data transfer by allowing a bursting data across the EISA bus at up to 33MBytes/second. The AIC-6251 has separate data buses for the local microprocessorand for the system data bus. This further increases the performance of the AHA-1740A/1742A/1744 by reducing the overhead associated with SCSI commands.8- and 16-Bit Memory and Odd Byte Data TransfersThe AHA-1740A/1742A/1744 will automatically shift to 8- or 16-bit data transfers asindicated by the control lines on the EISA bus. Bus master data transfers into 8- or16-bit wide memory are fully supported as are full 32-bit wide data transfers.During normal DMA operations, nearly all transfers to and from memory are 32-bittransfers. At the very end, or the very beginning of an odd address boundary, an 8-bit, 16-bit, or 24-bit transfer may occur.Bus Auxiliary Interface Chip (AIC-565)This highly integrated ASIC (Application Specific Integrated Circuit) device devel-oped by Adaptec is also used with the AHA-1540B host adapter family. It providesthe Standard Mode programming interface and implements the following main func-tional blocks:• Bus control interface for Standard Mode• Host adapter microprocessor interface• BIOS decode logicThe bus control interface section decodes the possible base addresses for the boardI/O port address, including a select external to the board. It also provides all registersused to communicate between the host adapter and the motherboard which are ac-cessed through the bus in Standard Mode. This ensures full compatibility with soft-ware written for the AHA-1540/1542 family of AT Bus Master Host Adapters.EISA-to-Fast SCSI Host Adapter Architecture2-3
