Chapter FourHardware Functional DescriptionHardware OverviewThis section provides a description of the AHA-1740A/1742A/1744 hardware fun-tional interface to the EISA host software.The hardware consists of:• Custom SCSI protocol chip• AIC-6251• EISA Interface Controller• Intel 82355• FIFO buffer• Set of I/O ports• Controlling microprocessor• AIC-565 Standard Mode control interface• AIC-575 AHA-1740 mode interfaceThe DMA control logic in the 82355 controls the bus arbitration and data transferhandshaking. During DMA data transfers, the AHA-1740A/1742A/1744 becomes abus master. The DMA logic supports odd- and even-byte and odd- and even-wordstarting addresses. For odd-byte starting addresses, the first transfer will be an 8-bittransfer, For odd-word starting address, the first transfer will be a 16-bit transfer.The SCSI port is controlled by the AIC-6251, and Adaptec SCSI protocol device forfast (10.0 MBytes/second transfers) which supports arbitration, selection, and reselec-tion with a minimum of processor intervention. This VLSI device also supports targetmode (simultaneous to initiator mode) and synchronous SCSI transfers.Standard Mode I/O Port InterfaceThe I/O port interface consists of three address locations. These three port addressesare decoded in the AT I/O address space. They form the primary communicationschannel between the host and the host adapter. The I/O ports are eight bits wide.4-1
