terminated abnormally. The use of CDF as a handshaking bit is required to preventthe transfer of invalid data.If an adapter command requires data transfer from the host adapter, the host adapt-er will place the data bytes in the Data In Port and set the DF bit (Status Port bit 2)to indicate that the requested parameter is ready for the host to read. When the hostreads the Data port, DF is automatically reset. The host should wait until DF isagain set before attempting to transfer the next parameter byte. The use of the DFbit to control the handshaking process is required to prevent the transfer of invaliddata. After the last data byte has been transferred, the HACC interrupt bit will beset indicating command completion. If the Adapter Command was invalid, the HACCinterrupt will occur before all data bytes have been transmitted and the INVDCMDbit will be set.Interrupt Flag PortThe Interrupt Flag Port contains bits that indicate the reason that an interrupt wasprovided to the host from the host adapter. The host adapter uses the interrupt to no-tify the host that the host adapter is ready for immediate service from the host. TheInterrupt Flag Port is a read-only port. When an interrupt bit is set by the host adapt-er to indicate that the host should respond, the Any Interrupt bit and the interruptline are both also set. When the host begins to examine the returned registers andmailboxes to determine the cause of the interrupt and to perform the operationsneeded to service the interrupt, the host will first read the Interrupt Flag Port to re-cord which interrupts must be serviced. The host will then clear the interrupts by set-ting the IRST bit (Host Adapter Control Port bit 5). The host adapter presents MBOAand MBIF interrupts immediately unless there is already an SCRD or HACC inter-rupt present. If the SCRD or HACC is present, the MBOA and/or MBIF interruptwill be posted after the SCRD or HACC interrupt is cleared. An SCRD or HACC in-terrupt will only be presented if the Any Interrupt signal is zero and the DF signal iszero, indicating the completion of all pending interrupt presentation. It is recom-mended that the MBOA interrupt be enabled only when required by the host. Thisprevents the possible presentation and resetting of MBIF interrupts before they areprocessed. Other reset operations will also reset the Interrupt Flag Port and the in-terrupt line, including the Hard Reset bit (HRST), the Soft Reset bit (SRST), and thepower-on reset issued by the motherboard.Base+2 Port, Read only: Interrupt Flag PortBit 7 - Any InterruptThis bit, when one, indicates that the interrupt to the host has been established. Theinterrupting condition is identified in bits 0 to 3.Bit 6 - ReservedReturned as zero.Bit 5 - ReservedReturned as zero.Bit 4 - ReservedReturned as zero.adaptec AHA-1740A/1742A/17444-6
