9-6 L90 Line Current Differential System GE Multilin9.1 OVERVIEW 9 THEORY OF OPERATION99.1.9 FREQUENCY TRACKING AND PHASE LOCKINGEach relay has a digital clock that determines when to take data samples and which is phase synchronized to all otherclocks in the system and frequency synchronized to the power system frequency. Phase synchronization drives the relativetiming error between clocks to zero, and is needed to control the uncertainty in the phase angle of phasor measurements,which will be held to under 26 microseconds (0.6 degrees). Frequency synchronization to the power system eliminates asource of error in phasor measurements that arises when data samples do not exactly span one cycle.The block diagram for clock control for a two terminal system is shown in the following figure. Each relay makes a local esti-mate of the difference between the power system frequency and the clock frequency based on the rotation of phasors.Each relay also makes a local estimate of the time difference between its clock and the other clocks either by exchangingtiming information over communications channels or from information that is in the current phasors, depending on which-ever one is more accurate at any given time. A loop filter then uses the frequency and phase angle deviation information tomake fine adjustments to the clock frequency. Frequency tracking starts if the current at one or more terminals is above0.125 pu of nominal; otherwise, the nominal frequency is used.Figure 9–1: BLOCK DIAGRAM FOR CLOCK SYNCHRONIZATION IN A TWO-TERMINAL SYSTEMThe L90 provides sensitive digital current differential protection by computing differential current from current phasors. Toimprove sensitivity, the clocks are controlling current sampling are closely synchronized via the ping-pong algorithm. How-ever, this algorithm assumes the communication channel delay is identical in each direction. If the delays are not the same,the error between current phasors is equal to half of the transmit-receive time difference. If the error is high enough, therelay perceives the “apparent” differential current and misoperates.For applications where the communication channel is not symmetric (for example, SONET ring), the L90 allows the use ofGPS (Global Positioning System) to compensate for the channel delay asymmetry. This feature requires a GPS receiver toprovide a GPS clock signal to the L90. With this option there are two clocks as each terminal: a local sampling clock and alocal GPS clock. The sampling clock controls data sampling while the GPS clock provides an accurate, absolute time refer-ence used to measure channel asymmetry. The local sampling clocks are synchronized to each other in phase and to thepower system in frequency. The local GPS clocks are synchronized to GPS time using the externally provided GPS timesignal.GPS time stamp is included in the transmitted packet along with the sampling clock time stamp. Both sampling clock devia-tion and channel asymmetry are computed from the four time-stamps. One half of the channel asymmetry is then sub-tracted from the computed sampling clock deviation. The compensated deviation drives the phase and frequency lock loop831026A1.CDR+( 2 – 1)/2ϕ ϕtime stampsSystemFrequencyComputeFrequencyDeviationPing-PongPhaseDeviationPhase FrequencyLoop Filterf+++_RELAY 1 RELAY 2f1f – f1GPSClockGPSPhaseDeviationϕ1θ( 2 – 1)/2θ θ+f+++_f2 f – f2ϕ2θtime stampsComputeFrequencyDeviationPhase FrequencyLoop FilterPing-PongPhaseDeviationGPSPhaseDeviationGPSClock( 2 – 1)/2ϕ ϕ( 2 – 1)/2θ θ
