2.2 DC SUPPLY MONITOR LOGICV01220Vdc1 Lower LimitEnabledVdc1 Upper LimitVdc1 StatusInhibitDC SupMon&Vdc1 StartVdc1 TripVdcVdct0Vdc1 Time DelayFigure 131: DC Supply Monitor logicThe diagram above shows the DC supply monitoring logic for stage 1 only. Stages 2 and 3 are identical in principle.The logic function will work when the Vdc1 status setting cell is Enabled and the DC Supply Monitoring inhibitsignal (InhibitDC SupMon) is low.If the auxiliary supply voltage (Vdc) exceeds the lower limit AND falls below the upper limit, the voltage is in thehealthy zone and a Start signal is generated.The Vdc(n) Trip signals from all stages are OR'd together to produce an alarm signal DC Supply Fail.Note:The device's supercapacitor uses Vdc to provide charge and so may cause the voltage to dip below the Vdc lower limit (19.2 V)during a system power-up sequence if fully discharged. This will trigger a lockout error. In this case, it will be necessary toallow the supercapacitor to charge before attempting another power-up sequence. The supercapacitor may take severalminutes to become fully charged, depending on the AC/DC supply specification. With the supercapacitor charged, the nextrelay power cycle will clear the lockout and the relay will boot and operate normally.P24xM Chapter 14 - SupervisionP24xM-TM-EN-2.1 275