NEC FP1355 Service Manual

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NEC FP1355 Service Manual Manual pdf 47 page image

1 - 411.6.10 Clamp pulseThe clamp pulse signal CLP is output from pin 22 of the MPU IC101 with the polarity POSI.When "2" is selected in the OSD adjustment item "EDGE LOCK", the signal is triggered at thefront edge of HSYNC, and when "1" is selected, the signal is triggered at the rear edge.1.6.11 SPARKIf it is electrically discharged in the CRT tube, the GND level of the high-voltage system circuitis considerably varied. GND of this high-voltage system is connected to the MPU IC101 pin 25via C103. The voltage level of MPU IC101 pin 25 is normally set at HI. If GND in the high-voltage system varies since it is electrically discharged in the CRT tube, the current will flow toR130 to set MPU IC101 pin 25 at the LO level. Pin 25 is the external interrupt terminal thatdetects the trailing edge. When the trailing edge is detected, the MPU forcibly applies S/WRESET. (It is the same as when the power SW is turned ON.)The above operation prevents the monitor from going out of control when it is electrically dis-charged in the CRT tube.1.6.12 Avoidance operation during input SYNC switchingThe horizontal LOCK output signal of the deflection processor IC601 pin 46 is connected to theMPU IC101 pin 23. MPU IC101 pin 23 is the external interrupt terminal of the trailing edgedetection. Though the voltage level of the LOCK signal is normally set at HI, IC601 outputs LOwhen the horizontal deflection lock is released since the input SYNC is switched.When the MPU detects the trailing edge, the HSK signal of IC101 pin 50 is set at HI, and thesimulative SYNC that is near the original frequency is output from pin 26 and pin 27. HSKsignal is used to set +B, voltage at MIN.This reduces the stress when the input SYNC is switched for a short time.1.6.13 CS switch and vertical linearity switchMicrocomputer IC101 outputs CS switch signal and vertical linearity switch signal via I/O ex-pander IC102, and corrects the linearity in the screen.Patterns of vertical linearity switch are shown in the table below.As for CS switch pattern, refer to Table 4.1.6.14 H/W RESETThe +5V power is connected to pin 2 of the voltage detector IC100, and IC100 pin 1 output isconnected to the MPU IC101 pin 54.On the voltage detector, pin 1 is the open drain output, being turned OFF when pin 2 voltage is4.5V or more, and ON when it is 4.5V or less. When the power switch is turned ON, IC100 pin1 is turned ON and the MPU pin 54 level is set at 0V since +5V has not started up.When the voltage of IC100 pin 2 becomes 4.5V or more, IC100 pin 1 will be turned OFF, andthe voltage of the MPU pin 54 rises with the time constants of R100 and C100.When the voltage of the MPU pin 54 becomes 3.5V or more, the MPU will start operating.Table 8 SW_VLIN1, SW_VLIN2 select pattern (IC102)Vertical frequency50Hz `77.9Hz78Hz `89.9Hz90Hz `124.9Hz125Hz `160HzSW-VLIN1Pin 12LOHILOHISW-VLIN2Pin 13LOLOHIHI