122CHAPTER 5 CPU ARCHITECTURE5.4 Operand Address AddressingThe following methods are available to specify the register and memory (addressing) which undergo manipulationduring instruction execution.5.4.1 Implied addressing[Function]The register which functions as an accumulator (A and AX) in the general register is automatically (implicitly)addressed.Of theμPD78078 and 78078Y Subseries instruction words, the following instructions employ implied addressing.Instruction Register to be Specified by Implied AddressingMULU A register for multiplicand and AX register for product storageDIVUW AX register for dividend and quotient storageADJBA/ADJBS A register for storage of numeric values which become decimal correction targetsROR4/ROL4 A register for storage of digit data which undergoes digit rotation[Operand format]Because implied addressing can be automatically employed with an instruction, no particular operand format isnecessary.[Description example]In the case of MULU XWith an 8-bit x 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example,the A and AX registers are specified by implied addressing.
