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NEC PD78076 User Manual

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. Table Of Contents
  17. Table Of Contents
  18. Table Of Contents
  19. Table Of Contents
  20. Table Of Contents
  21. Features
  22. Application Fields
  23. Quality Grade
  24. Pin Configuration (Top View)
  25. K/0 Series Expansion
  26. Block Diagram
  27. Outline of Function
  28. Mask Options
  29. CHAPTER 2 OUTLINE ( PD78078Y SUBSERIES)
  30. Ordering Information
  36. Differences with PD78054Y Subseries
  37. Pin Function List
  38. PROM programming mode pins ( PD78P078 only)
  39. Description of Pin Functions
  40. P20 to P27 (Port 2)
  41. P30 to P37 (Port 3)
  42. P50 to P57 (Port 5)
  43. P70 to P72 (Port 7)
  44. P90 to P96 (Port 9)
  45. P130 and P131 (Port 13)
  46. IC (Mask ROM version only)
  47. Input/output Circuits and Recommended Connection of Unused Pins
  48. List of Pin Input/Output Circuits
  49. CHAPTER 4 PIN FUNCTION ( PD78078Y SUBSERIES)
  50. PROM programming mode pins ( PD78P078Y only)
  51. P00 to P07 (Port 0)
  53. P40 to P47 (Port 4)
  54. P60 to P67 (Port 6)
  55. P80 to P87 (Port 8)
  56. P100 to P103 (Port 10)
  57. AV REF0
  59. Pin Input/Output Circuit Types
  61. Memory Spaces
  62. Memory Map ( PD78078, 78078Y)
  63. Memory Map ( PD78P078, PD78P078Y)
  64. Internal program memory space
  65. Vector Table
  66. Internal data memory space
  67. Data memory addressing
  68. Data Memory Addressing ( PD78078, 78078Y)
  69. Data Memory Addressing ( PD78P078, 78P078Y)
  70. Processor Registers
  71. Stack Pointer Configuration
  72. General registers
  73. Special function register (SFR)
  74. Special Function Register List
  75. Instruction Address Addressing
  76. Immediate addressing
  77. Table indirect addressing
  78. Register addressing
  79. Operand Address Addressing
  81. Direct addressing
  82. Short direct addressing
  83. Special function register (SFR) addressing
  84. Register indirect addressing
  85. Based addressing
  86. Based indexed addressing
  87. Port Functions
  88. Port Functions ( PD78078 Subseries)
  89. Port Functions ( PD78078Y Subseries)
  90. Port Configuration
  91. Block Diagram of P00 and P07
  92. Port 1
  93. Port 2 ( PD78078 Subseries)
  94. Block Diagram of P22 and P27
  95. Port 2 ( PD78078Y Subseries)
  97. Port 3
  98. Port 4
  99. Port 5
  100. Port 6
  101. Block Diagram of P60 to P63
  102. Port 7
  103. Block Diagram of P71 and P72
  104. Port 8
  105. Port 9
  106. Block Diagram of P90 to P93
  107. Port 10
  108. Block Diagram of P102 and P103
  109. Port 12
  110. Port 13
  111. Port Function Control Registers
  112. Port Mode Register and Output Latch Settings when Using Alternate Function
  113. Port Mode Register Format
  114. Pull-Up Resistor Option Register Format
  115. Memory Expansion Mode Register Format
  116. Key Return Mode Register Format
  117. Port Function Operations
  118. Selection of Mask Option
  119. Clock Generator Functions
  120. Clock Generator Configuration
  121. Clock Generator Control Register
  122. Processor Clock Control Register Format
  123. Relationship between CPU Clock and Minimum Instruction Execution Time
  124. Oscillation Mode Selection Register Format
  125. System Clock Oscillator
  126. Subsystem clock oscillator
  127. Divider
  128. Clock Generator Operations
  129. Main system clock operations
  130. Subsystem clock operations
  131. Changing System Clock and CPU Clock Settings
  132. System clock and CPU clock switching procedure
  133. Outline of Timers Incorporated into PD78078, 78078Y Subseries
  134. Timer/Event Counter Operations
  135. Bit Timer/Event Counter Functions
  136. Bit Timer/Event Counter Square-Wave Output Ranges
  137. Bit Timer/Event Counter Configuration
  138. Bit Timer/Event Counter Block Diagram
  139. Bit Timer/Event Counter Output Control Circuit Block Diagram
  140. INTP0/TI00 Pin Valid Edge and CR00 Capture Trigger Valid Edge
  141. Bit Timer/Event Counter Control Registers
  142. Timer Clock Selection Register 0 Format
  143. Bit Timer Mode Control Register Format
  144. Capture/Compare Control Register 0 Format
  145. Bit Timer Output Control Register Format
  146. Port Mode Register 3 Format
  147. External Interrupt Mode Register 0 Format
  148. Sampling Clock Select Register Format
  149. Bit Timer/Event Counter Operations
  150. Interval Timer Configuration Diagram
  151. PWM output operations
  152. Control Register Settings for PWM Output Operation
  153. Example of D/A Converter Configuration with PWM Output
  154. PPG output operations
  155. Pulse width measurement operations
  156. Configuration Diagram for Pulse Width Measurement by Free-Running Counter
  157. Control Register Settings for Two Pulse Width Measurements with Free-Running Counter
  158. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified)
  159. Control Register Settings for Pulse Width Measurement by Means of Restart
  160. External event counter operation
  161. External Event Counter Configuration Diagram
  162. Square-wave output operation
  163. Square-Wave Output Operation Timing
  164. One-shot pulse output operation
  165. Timing of One-Shot Pulse Output Operation Using Software Trigger
  166. Control Register Settings for One-Shot Pulse Output Operation Using External Trigger
  167. Bit Timer/Event Counter Operating Precautions
  168. Capture Register Data Retention Timing
  169. Operation Timing of OVF0 Flag
  170. Bit Timer/Event Counters 1 and 2 Functions
  171. Bit Timer/Event Counters 1 and 2 Interval Times
  172. Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges
  173. bit timer/event counter mode
  174. Square-Wave Output Ranges when 8-Bit Timer/Event Counters 1 and 2 are Used as 16-Bit Timer/Event Counters
  175. Bit Timer/Event Counters 1 and 2 Configurations
  176. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1
  177. Bit Timer/Event Counters 1 and 2 Control Registers
  178. Timer Clock Select Register 1 Format
  179. Bit Timer Mode Control Register 1 Format
  182. Bit Timer/Event Counters 1 and 2 Operations
  183. Bit Timer/Event Counter 1 Interval Time
  184. Bit Timer/Event Counter 2 Interval Time
  185. External Event Counter Operation Timings (with Rising Edge Specified)
  187. Timing of Square Wave Output Operation
  188. Interval Timer Operation Timing
  189. are Used as 16-Bit Timer/Event Counter
  191. Square-Wave Output Ranges when 2-Channel 8-Bit Timer/Event Counters TM1 and TM2) are Used as 16-Bit Timer/Event Counter
  192. Bit Timer/Event Counters 1 and 2 Precautions
  193. Timing after Compare Register Change during Timer Count Operation
  194. CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6
  195. Bit Timer/Event Counters 5 and 6 Interval Times
  196. Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges
  197. Bit Timer/Event Counters 5 and 6 Configurations
  198. Block Diagram of 8-Bit Timer/Event Counters 5 and 6 Output Control Circuit
  199. Bit Timer/Event Counters 5 and 6 Control Registers
  200. Timer Clock Select Register 6 Format
  202. Bit Timer Output Control Register 6 Format
  203. Port Mode Register 10 Format
  204. Bit Timer/Event Counters 5 and 6 Operations
  206. Bit Timer Mode Control Register Setting for External Event Counter Operation
  207. Square-wave output
  209. Bit Timer Control Register Settings for PWM Output Operation
  210. PWM Output Operation Timing (Active High Setting)
  211. PWM Output Operation Timings (CRn0 = FFH, Active High Setting)
  212. Bit Timer/Event Counters 5 and 6 Precautions
  213. Timings after Compare Register Change during Timer Count Operation
  214. CHAPTER 11 WATCH TIMER
  215. Watch Timer Configuration
  216. Watch Timer Control Registers
  217. Timer Clock Select Register 2 Format
  218. Watch Timer Mode Control Register Format
  219. Watch Timer Operations
  220. CHAPTER 12 WATCHDOG TIMER
  221. Interval Times
  222. Watchdog Timer Configuration
  223. Watchdog Timer Control Registers
  225. Watchdog Timer Mode Register Format
  226. Watchdog Timer Operations
  227. Interval timer operation
  228. CHAPTER 13 CLOCK OUTPUT CONTROL CIRCUIT
  229. Clock Output Control Circuit Configuration
  230. Clock Output Function Control Registers
  231. Timer Clock Select Register 0 Format
  233. CHAPTER 14 BUZZER OUTPUT CONTROL CIRCUIT
  234. Buzzer Output Function Control Registers
  237. CHAPTER 15 A/D CONVERTER
  238. A/D Converter Block Diagram
  239. A/D Converter Control Registers
  240. A/D Converter Mode Register Format
  241. A/D Converter Input Select Register Format
  242. External Interrupt Mode Register 1 Format
  243. A/D Converter Operations
  244. A/D Converter Basic Operation
  245. Input voltage and conversion results
  246. A/D converter operating mode
  247. A/D Conversion by Software Start
  248. A/D Converter Cautions
  249. Analog Input Pin Disposition
  250. A/D Conversion End Interrupt Request Generation Timing
  251. CHAPTER 16 D/A CONVERTER
  252. D/A Converter Configuration
  253. D/A Converter Control Registers
  254. D/A Converter Operations
  255. D/A Converter Cautions
  256. CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES)
  257. Serial Interface Channel 0 Functions
  258. Serial Bus Interface (SBI) System Configuration Example
  259. Serial Interface Channel 0 Configuration
  260. Serial Interface Channel 0 Control Registers
  261. Timer Clock Select Register 3 Format
  262. Serial Operating Mode Register 0 Format
  263. Serial Bus Interface Control Register Format
  264. Interrupt Timing Specify Register Format
  265. Serial Interface Channel 0 Operations
  266. wire serial I/O mode operation
  267. Wire Serial I/O Mode Timings
  268. Circuit of Switching in Transfer Bit Order
  269. SBI mode operation
  270. SBI Transfer Timings
  271. Bus Release Signal
  272. Addresses
  273. Commands
  274. Acknowledge Signal
  275. RELT, CMDT, RELD, and CMDD Operations (Master)
  276. ACKT Operation
  277. ACKE Operations
  278. ACKD Operations
  279. Various Signals in SBI Mode
  280. Pin Configuration
  281. Address Transmission from Master Device to Slave Device (WUP = 1)
  282. Command Transmission from Master Device to Slave Device
  283. Data Transmission from Master Device to Slave Device
  284. Data Transmission from Slave Device to Master Device
  285. Serial Bus Configuration Example Using 2-Wire Serial I/O Mode
  286. RELT and CMDT Operations
  287. SCK0/P27 pin output manipulation
  288. CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries)
  291. Serial Interface Channel 0 Block Diagram
  292. Serial Interface Channel 0 Interrupt Request Signal Generation
  298. Operation stop mode
  305. I 2 C bus mode operation
  306. I 2 C Bus Serial Data Transfer Timing
  307. Start Condition
  308. Stop Condition
  309. Wait Signal
  311. Start Condition Output
  312. Slave Wait Release (Transmission)
  313. Slave Wait Release (Reception)
  314. Restrictions in I 2 C bus mode
  315. SCK0/SCL/P27 pin output manipulation
  316. SCK0/SCL/P27 Pin Configuration
  317. CHAPTER 19 SERIAL INTERFACE CHANNEL 1
  318. Serial Interface Channel 1 Configuration
  319. Serial Interface Channel 1 Control Registers
  320. Serial Operation Mode Register 1 Format
  321. Automatic Data Transmit/Receive Control Register Format
  322. Automatic Data Transmit/Receive Interval Specify Register Format
  323. Serial Interface Channel 1 Operations
  327. wire serial I/O mode operation with automatic transmit/receive function
  328. Basic Transmission/Reception Mode Operation Timings
  329. Basic Transmission/Reception Mode Flowchart
  330. Basic Transmission Mode Operation Timings
  331. Basic Transmission Mode Flowchart
  332. Buffer RAM Operation in 6-byte Transmission (in Basic Transmit Mode)
  333. Repeat Transmission Mode Operation Timing
  334. Repeat Transmission Mode Flowchart
  335. Buffer RAM Operation in 6-byte Transmission (in Repeat Transmit mode)
  336. Automatic Transmission/Reception Suspension and Restart
  337. System Configuration when the Busy Control Option is Used
  338. Operation Timings when Using Busy Control Option (BUSY0 = 0)
  339. Busy Signal and Wait Cancel (BUSY0 = 0)
  340. Operation Timings when Using Busy & Strobe Control Option (BUSY0 = 0)
  341. Automatic Data Transmit/Receive Interval
  342. Operation Timing with Automatic Data Transmit/Receive Function Performed by Internal Clock
  343. Interval Timing through CPU Processing (when the External Clock is Operating)
  344. CHAPTER 20 SERIAL INTERFACE CHANNEL 2
  345. Serial Interface Channel 2 Configuration
  346. Baud Rate Generator Block Diagram
  347. Serial Interface Channel 2 Control Registers
  348. Asynchronous Serial Interface Mode Register Format
  349. Serial Interface Channel 2 Operating Mode Settings
  350. Asynchronous Serial Interface Status Register Format
  351. Baud Rate Generator Control Register Format
  352. Relationship between Main System Clock and Baud Rate
  353. Serial Interface Channel 2 Operation
  354. Asynchronous serial interface (UART) mode
  356. Asynchronous Serial Interface Transmit/Receive Data Format
  357. Asynchronous Serial Interface Transmission Completion Interrupt Request Generation Timing
  358. Asynchronous Serial Interface Reception Completion Interrupt Request Generation Timing
  359. Receive Error Timing
  360. State of Receive Buffer Register (RXB) When Receive Operation is Stopped and Whether Interrupt Request (INTSR) is Generated or Not
  361. wire serial I/O mode
  362. Wire Serial I/O Mode Timing
  364. Restrictions on using UART mode
  365. Period that Reading Receive Buffer Register is Prohibited
  366. CHAPTER 21 REAL-TIME OUTPUT PORT
  367. Real-time Output Buffer Register Configuration
  368. Real-Time Output Port Control Registers
  369. Real-time Output Port Control Register Format
  370. CHAPTER 22 INTERRUPT FUNCTIONS
  371. Interrupt Sources and Configuration
  372. Basic Configuration of Interrupt Function
  373. Interrupt Function Control Registers
  374. Interrupt Request Flag Register Format
  375. Interrupt Mask Flag Register Format
  376. Priority Specify Flag Register Format
  380. Noise Eliminator Input/Output Timing (during Rising Edge Detection)
  381. Program Status Word Format
  382. Interrupt Servicing Operations
  383. Flowchart from Non-Maskable Interrupt Generation to Acknowledge
  384. Non-Maskable Interrupt Request Acknowledge Operation
  385. Maskable interrupt request acknowledge operation
  386. Interrupt Request Acknowledge Processing Algorithm
  387. Software interrupt request acknowledge operation
  388. Multiple interrupt servicing
  389. Multiple Interrupt Example
  390. Interrupt request reserve
  391. Test Functions
  392. Format of Interrupt Request Flag Register 1L
  393. Test input signal acknowledge operation
  394. CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION
  395. Pin Functions in Separate Bus Mode
  396. Memory Map when Using External Device Expansion Function
  397. External Device Expansion Function Control Register
  398. Internal Memory Size Switching Register Format
  399. External Bus Type Select Register Format
  400. External Device Expansion Function Timing
  401. Instruction Fetch from External Memory in Multiplexed Bus Mode
  402. External Memory Read Timing in Multiplexed Bus Mode
  403. External Memory Write Timing in Multiplexed Bus Mode
  404. External Memory Read Modify Write Timing in Multiplexed Bus Mode
  405. Timings in separate bus mode
  406. Instruction Fetch from External Memory in Separate Bus Mode
  407. External Memory Read Timing in Separate Bus Mode
  408. External Memory Write Timing in Separate Bus Mode
  409. External Memory Read Modify Write Timing in Separate Bus Mode
  410. CHAPTER 24 STANDBY FUNCTION
  411. Standby function control register
  412. Standby Function Operations
  413. HALT Mode Released by Interrupt Request Generation
  414. HALT Mode Released by RESET Input
  415. STOP mode
  416. STOP Mode Released by Interrupt Request Generation
  417. STOP Mode Released by RESET Input
  418. CHAPTER 25 RESET FUNCTION
  419. Timing of Reset by RESET Input
  420. Hardware Status after Reset
  421. CHAPTER 26 ROM CORRECTION
  422. Correction Address Registers 0 and 1 Format
  423. ROM Correction Control Registers
  424. ROM Correction Application
  425. Initialization Routine
  426. ROM Correction Operation
  427. ROM Correction Example
  428. Program Execution Flow
  429. Program Transition Diagram (when Two Places are Corrected)
  430. Cautions on ROM Correction
  431. CHAPTER 27 PD78P078, 78P078Y
  432. Internal Memory Size Switching Register
  433. Internal Extension RAM Size Switching Register
  434. PROM Programming
  435. PROM write procedure
  436. Page Program Mode Timing
  437. Byte Program Mode Flowchart
  438. Byte Program Mode Timing
  439. PROM reading procedure
  440. Erasure Procedure ( PD78P078KL-T and 78P078YKL-T Only)
  441. CHAPTER 28 INSTRUCTION SET
  442. Legends Used in Operation List
  443. Description of "operation" column
  444. Operation List
  445. Instructions Listed by Addressing Type
  446. APPENDIX A DIFFERENCES BETWEEN PD78078, 78075B SUBSERIES, AND PD78070A
  447. APPENDIX B DEVELOPMENT TOOLS
  448. B-1 Development Tool Configuration
  449. B.1 Language Processing Software
  450. B.2 PROM Writing Tools
  451. B.3 Debugging Tools
  452. B.3.2 Software
  453. B.5 System Upgrading from Former-type In-circuit Emulator for 78K/0 Series to IE-78001-R-A
  454. B-2 TGC-100SDW Drawing (For Reference Only)
  455. B-3 EV-9200GF-100 Drawing (For Reference Only)
  456. B-4 EV-9200GF-100 Recommended Footprints (For Reference Only)
  457. APPENDIX C EMBEDDED SOFTWARE
  458. APPENDIX D REGISTER INDEX
  459. D.2 Register Symbol Index
  460. APPENDIX E REVISION HISTORY
NEC PD78076 User Manual Manual pdf 80 page image
80CHAPTER 3 PIN FUNCTION (μPD78078 SUBSERIES)Figure 3-1. List of Pin Input/Output Circuits (1/2)INpullupenableVDDP-chIN/OUTinputenableoutputdisabledataVDDP-chN-chType 2Type 5-ASchmitt-Triggered Input withHysteresis CharacteristicsType 5-E Type 11Type 10-AType 8-ApullupenableVDDP-chIN/OUToutputdisabledataVDDP-chN-chpullupenableVDDP-chIN/OUToutputdisabledataVDDP-chN-chpullupenableVDDP-chIN/OUTopen drainoutput disabledataVDDP-chN-chpullupenableVDDP-chIN/OUToutputdisabledataVDDP-chN-chP-chcomparatorN-chinputenableVREF (Threshold voltage)+–
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This manual is suitable for:
PD78076PD78076YPD78078PD78078YPD78P078PD78P078YuPD78076uPD78076YuPD78078uPD78078YuPD78P078uPD78P078Y
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