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NEC PD78076 User Manual

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. Table Of Contents
  17. Table Of Contents
  18. Table Of Contents
  19. Table Of Contents
  20. Table Of Contents
  21. Features
  22. Application Fields
  23. Quality Grade
  24. Pin Configuration (Top View)
  25. K/0 Series Expansion
  26. Block Diagram
  27. Outline of Function
  28. Mask Options
  29. CHAPTER 2 OUTLINE ( PD78078Y SUBSERIES)
  30. Ordering Information
  31. Differences with PD78054Y Subseries
  32. Pin Function List
  33. PROM programming mode pins ( PD78P078 only)
  34. Description of Pin Functions
  35. P20 to P27 (Port 2)
  36. P30 to P37 (Port 3)
  37. P50 to P57 (Port 5)
  38. P70 to P72 (Port 7)
  39. P90 to P96 (Port 9)
  40. P130 and P131 (Port 13)
  41. IC (Mask ROM version only)
  42. Input/output Circuits and Recommended Connection of Unused Pins
  43. List of Pin Input/Output Circuits
  44. CHAPTER 4 PIN FUNCTION ( PD78078Y SUBSERIES)
  45. PROM programming mode pins ( PD78P078Y only)
  46. P00 to P07 (Port 0)
  47. P40 to P47 (Port 4)
  48. P60 to P67 (Port 6)
  49. P80 to P87 (Port 8)
  50. P100 to P103 (Port 10)
  51. AV REF0
  52. Pin Input/Output Circuit Types
  53. Memory Spaces
  54. Memory Map ( PD78078, 78078Y)
  55. Memory Map ( PD78P078, PD78P078Y)
  56. Internal program memory space
  57. Vector Table
  58. Internal data memory space
  59. Data memory addressing
  60. Data Memory Addressing ( PD78078, 78078Y)
  61. Data Memory Addressing ( PD78P078, 78P078Y)
  62. Processor Registers
  63. Stack Pointer Configuration
  64. General registers
  65. Special function register (SFR)
  66. Special Function Register List
  67. Instruction Address Addressing
  68. Immediate addressing
  69. Table indirect addressing
  70. Register addressing
  71. Operand Address Addressing
  72. Direct addressing
  73. Short direct addressing
  74. Special function register (SFR) addressing
  75. Register indirect addressing
  76. Based addressing
  77. Based indexed addressing
  78. Port Functions
  79. Port Functions ( PD78078 Subseries)
  80. Port Functions ( PD78078Y Subseries)
  81. Port Configuration
  82. Block Diagram of P00 and P07
  83. Port 1
  84. Port 2 ( PD78078 Subseries)
  85. Block Diagram of P22 and P27
  86. Port 2 ( PD78078Y Subseries)
  87. Port 3
  88. Port 4
  89. Port 5
  90. Port 6
  91. Block Diagram of P60 to P63
  92. Port 7
  93. Block Diagram of P71 and P72
  94. Port 8
  95. Port 9
  96. Block Diagram of P90 to P93
  97. Port 10
  98. Block Diagram of P102 and P103
  99. Port 12
  100. Port 13
  101. Port Function Control Registers
  102. Port Mode Register and Output Latch Settings when Using Alternate Function
  103. Port Mode Register Format
  104. Pull-Up Resistor Option Register Format
  105. Memory Expansion Mode Register Format
  106. Key Return Mode Register Format
  107. Port Function Operations
  108. Selection of Mask Option
  109. Clock Generator Functions
  110. Clock Generator Configuration
  111. Clock Generator Control Register
  112. Processor Clock Control Register Format
  113. Relationship between CPU Clock and Minimum Instruction Execution Time
  114. Oscillation Mode Selection Register Format
  115. System Clock Oscillator
  116. Subsystem clock oscillator
  117. Divider
  118. Clock Generator Operations
  119. Main system clock operations
  120. Subsystem clock operations
  121. Changing System Clock and CPU Clock Settings
  122. System clock and CPU clock switching procedure
  123. Outline of Timers Incorporated into PD78078, 78078Y Subseries
  124. Timer/Event Counter Operations
  125. Bit Timer/Event Counter Functions
  126. Bit Timer/Event Counter Square-Wave Output Ranges
  127. Bit Timer/Event Counter Configuration
  128. Bit Timer/Event Counter Block Diagram
  129. Bit Timer/Event Counter Output Control Circuit Block Diagram
  130. INTP0/TI00 Pin Valid Edge and CR00 Capture Trigger Valid Edge
  131. Bit Timer/Event Counter Control Registers
  132. Timer Clock Selection Register 0 Format
  133. Bit Timer Mode Control Register Format
  134. Capture/Compare Control Register 0 Format
  135. Bit Timer Output Control Register Format
  136. Port Mode Register 3 Format
  137. External Interrupt Mode Register 0 Format
  138. Sampling Clock Select Register Format
  139. Bit Timer/Event Counter Operations
  140. Interval Timer Configuration Diagram
  141. PWM output operations
  142. Control Register Settings for PWM Output Operation
  143. Example of D/A Converter Configuration with PWM Output
  144. PPG output operations
  145. Pulse width measurement operations
  146. Configuration Diagram for Pulse Width Measurement by Free-Running Counter
  147. Control Register Settings for Two Pulse Width Measurements with Free-Running Counter
  148. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified)
  149. Control Register Settings for Pulse Width Measurement by Means of Restart
  150. External event counter operation
  151. External Event Counter Configuration Diagram
  152. Square-wave output operation
  153. Square-Wave Output Operation Timing
  154. One-shot pulse output operation
  155. Timing of One-Shot Pulse Output Operation Using Software Trigger
  156. Control Register Settings for One-Shot Pulse Output Operation Using External Trigger
  157. Bit Timer/Event Counter Operating Precautions
  158. Capture Register Data Retention Timing
  159. Operation Timing of OVF0 Flag
  160. Bit Timer/Event Counters 1 and 2 Functions
  161. Bit Timer/Event Counters 1 and 2 Interval Times
  162. Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges
  163. bit timer/event counter mode
  164. Square-Wave Output Ranges when 8-Bit Timer/Event Counters 1 and 2 are Used as 16-Bit Timer/Event Counters
  165. Bit Timer/Event Counters 1 and 2 Configurations
  166. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1
  167. Bit Timer/Event Counters 1 and 2 Control Registers
  168. Timer Clock Select Register 1 Format
  169. Bit Timer Mode Control Register 1 Format
  170. Bit Timer/Event Counters 1 and 2 Operations
  171. Bit Timer/Event Counter 1 Interval Time
  172. Bit Timer/Event Counter 2 Interval Time
  173. External Event Counter Operation Timings (with Rising Edge Specified)
  174. Timing of Square Wave Output Operation
  175. Interval Timer Operation Timing
  176. are Used as 16-Bit Timer/Event Counter
  177. Square-Wave Output Ranges when 2-Channel 8-Bit Timer/Event Counters TM1 and TM2) are Used as 16-Bit Timer/Event Counter
  178. Bit Timer/Event Counters 1 and 2 Precautions
  179. Timing after Compare Register Change during Timer Count Operation
  180. CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6
  181. Bit Timer/Event Counters 5 and 6 Interval Times
  182. Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges
  183. Bit Timer/Event Counters 5 and 6 Configurations
  184. Block Diagram of 8-Bit Timer/Event Counters 5 and 6 Output Control Circuit
  185. Bit Timer/Event Counters 5 and 6 Control Registers
  186. Timer Clock Select Register 6 Format
  187. Bit Timer Output Control Register 6 Format
  188. Port Mode Register 10 Format
  189. Bit Timer/Event Counters 5 and 6 Operations
  190. Bit Timer Mode Control Register Setting for External Event Counter Operation
  191. Square-wave output
  192. Bit Timer Control Register Settings for PWM Output Operation
  193. PWM Output Operation Timing (Active High Setting)
  194. PWM Output Operation Timings (CRn0 = FFH, Active High Setting)
  195. Bit Timer/Event Counters 5 and 6 Precautions
  196. Timings after Compare Register Change during Timer Count Operation
  197. CHAPTER 11 WATCH TIMER
  198. Watch Timer Configuration
  199. Watch Timer Control Registers
  200. Timer Clock Select Register 2 Format
  201. Watch Timer Mode Control Register Format
  202. Watch Timer Operations
  203. CHAPTER 12 WATCHDOG TIMER
  204. Interval Times
  205. Watchdog Timer Configuration
  206. Watchdog Timer Control Registers
  207. Watchdog Timer Mode Register Format
  208. Watchdog Timer Operations
  209. Interval timer operation
  210. CHAPTER 13 CLOCK OUTPUT CONTROL CIRCUIT
  211. Clock Output Control Circuit Configuration
  212. Clock Output Function Control Registers
  213. Timer Clock Select Register 0 Format
  214. CHAPTER 14 BUZZER OUTPUT CONTROL CIRCUIT
  215. Buzzer Output Function Control Registers
  216. CHAPTER 15 A/D CONVERTER
  217. A/D Converter Block Diagram
  218. A/D Converter Control Registers
  219. A/D Converter Mode Register Format
  220. A/D Converter Input Select Register Format
  221. External Interrupt Mode Register 1 Format
  222. A/D Converter Operations
  223. A/D Converter Basic Operation
  224. Input voltage and conversion results
  225. A/D converter operating mode
  226. A/D Conversion by Software Start
  227. A/D Converter Cautions
  228. Analog Input Pin Disposition
  229. A/D Conversion End Interrupt Request Generation Timing
  230. CHAPTER 16 D/A CONVERTER
  231. D/A Converter Configuration
  232. D/A Converter Control Registers
  233. D/A Converter Operations
  234. D/A Converter Cautions
  235. CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES)
  236. Serial Interface Channel 0 Functions
  237. Serial Bus Interface (SBI) System Configuration Example
  238. Serial Interface Channel 0 Configuration
  239. Serial Interface Channel 0 Control Registers
  240. Timer Clock Select Register 3 Format
  241. Serial Operating Mode Register 0 Format
  242. Serial Bus Interface Control Register Format
  243. Interrupt Timing Specify Register Format
  244. Serial Interface Channel 0 Operations
  245. wire serial I/O mode operation
  246. Wire Serial I/O Mode Timings
  247. Circuit of Switching in Transfer Bit Order
  248. SBI mode operation
  249. SBI Transfer Timings
  250. Bus Release Signal
  251. Addresses
  252. Commands
  253. Acknowledge Signal
  254. RELT, CMDT, RELD, and CMDD Operations (Master)
  255. ACKT Operation
  256. ACKE Operations
  257. ACKD Operations
  258. Various Signals in SBI Mode
  259. Pin Configuration
  260. Address Transmission from Master Device to Slave Device (WUP = 1)
  261. Command Transmission from Master Device to Slave Device
  262. Data Transmission from Master Device to Slave Device
  263. Data Transmission from Slave Device to Master Device
  264. Serial Bus Configuration Example Using 2-Wire Serial I/O Mode
  265. RELT and CMDT Operations
  266. SCK0/P27 pin output manipulation
  267. CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries)
  268. Serial Interface Channel 0 Block Diagram
  269. Serial Interface Channel 0 Interrupt Request Signal Generation
  270. Operation stop mode
  271. I 2 C bus mode operation
  272. I 2 C Bus Serial Data Transfer Timing
  273. Start Condition
  274. Stop Condition
  275. Wait Signal
  276. Start Condition Output
  277. Slave Wait Release (Transmission)
  278. Slave Wait Release (Reception)
  279. Restrictions in I 2 C bus mode
  280. SCK0/SCL/P27 pin output manipulation
  281. SCK0/SCL/P27 Pin Configuration
  282. CHAPTER 19 SERIAL INTERFACE CHANNEL 1
  283. Serial Interface Channel 1 Configuration
  284. Serial Interface Channel 1 Control Registers
  285. Serial Operation Mode Register 1 Format
  286. Automatic Data Transmit/Receive Control Register Format
  287. Automatic Data Transmit/Receive Interval Specify Register Format
  288. Serial Interface Channel 1 Operations
  289. wire serial I/O mode operation with automatic transmit/receive function
  290. Basic Transmission/Reception Mode Operation Timings
  291. Basic Transmission/Reception Mode Flowchart
  292. Basic Transmission Mode Operation Timings
  293. Basic Transmission Mode Flowchart
  294. Buffer RAM Operation in 6-byte Transmission (in Basic Transmit Mode)
  295. Repeat Transmission Mode Operation Timing
  296. Repeat Transmission Mode Flowchart
  297. Buffer RAM Operation in 6-byte Transmission (in Repeat Transmit mode)
  298. Automatic Transmission/Reception Suspension and Restart
  299. System Configuration when the Busy Control Option is Used
  300. Operation Timings when Using Busy Control Option (BUSY0 = 0)
  301. Busy Signal and Wait Cancel (BUSY0 = 0)
  302. Operation Timings when Using Busy & Strobe Control Option (BUSY0 = 0)
  303. Automatic Data Transmit/Receive Interval
  304. Operation Timing with Automatic Data Transmit/Receive Function Performed by Internal Clock
  305. Interval Timing through CPU Processing (when the External Clock is Operating)
  306. CHAPTER 20 SERIAL INTERFACE CHANNEL 2
  307. Serial Interface Channel 2 Configuration
  308. Baud Rate Generator Block Diagram
  309. Serial Interface Channel 2 Control Registers
  310. Asynchronous Serial Interface Mode Register Format
  311. Serial Interface Channel 2 Operating Mode Settings
  312. Asynchronous Serial Interface Status Register Format
  313. Baud Rate Generator Control Register Format
  314. Relationship between Main System Clock and Baud Rate
  315. Serial Interface Channel 2 Operation
  316. Asynchronous serial interface (UART) mode
  317. Asynchronous Serial Interface Transmit/Receive Data Format
  318. Asynchronous Serial Interface Transmission Completion Interrupt Request Generation Timing
  319. Asynchronous Serial Interface Reception Completion Interrupt Request Generation Timing
  320. Receive Error Timing
  321. State of Receive Buffer Register (RXB) When Receive Operation is Stopped and Whether Interrupt Request (INTSR) is Generated or Not
  322. wire serial I/O mode
  323. Wire Serial I/O Mode Timing
  324. Restrictions on using UART mode
  325. Period that Reading Receive Buffer Register is Prohibited
  326. CHAPTER 21 REAL-TIME OUTPUT PORT
  327. Real-time Output Buffer Register Configuration
  328. Real-Time Output Port Control Registers
  329. Real-time Output Port Control Register Format
  330. CHAPTER 22 INTERRUPT FUNCTIONS
  331. Interrupt Sources and Configuration
  332. Basic Configuration of Interrupt Function
  333. Interrupt Function Control Registers
  334. Interrupt Request Flag Register Format
  335. Interrupt Mask Flag Register Format
  336. Priority Specify Flag Register Format
  337. Noise Eliminator Input/Output Timing (during Rising Edge Detection)
  338. Program Status Word Format
  339. Interrupt Servicing Operations
  340. Flowchart from Non-Maskable Interrupt Generation to Acknowledge
  341. Non-Maskable Interrupt Request Acknowledge Operation
  342. Maskable interrupt request acknowledge operation
  343. Interrupt Request Acknowledge Processing Algorithm
  344. Software interrupt request acknowledge operation
  345. Multiple interrupt servicing
  346. Multiple Interrupt Example
  347. Interrupt request reserve
  348. Test Functions
  349. Format of Interrupt Request Flag Register 1L
  350. Test input signal acknowledge operation
  351. CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION
  352. Pin Functions in Separate Bus Mode
  353. Memory Map when Using External Device Expansion Function
  354. External Device Expansion Function Control Register
  355. Internal Memory Size Switching Register Format
  356. External Bus Type Select Register Format
  357. External Device Expansion Function Timing
  358. Instruction Fetch from External Memory in Multiplexed Bus Mode
  359. External Memory Read Timing in Multiplexed Bus Mode
  360. External Memory Write Timing in Multiplexed Bus Mode
  361. External Memory Read Modify Write Timing in Multiplexed Bus Mode
  362. Timings in separate bus mode
  363. Instruction Fetch from External Memory in Separate Bus Mode
  364. External Memory Read Timing in Separate Bus Mode
  365. External Memory Write Timing in Separate Bus Mode
  366. External Memory Read Modify Write Timing in Separate Bus Mode
  367. CHAPTER 24 STANDBY FUNCTION
  368. Standby function control register
  369. Standby Function Operations
  370. HALT Mode Released by Interrupt Request Generation
  371. HALT Mode Released by RESET Input
  372. STOP mode
  373. STOP Mode Released by Interrupt Request Generation
  374. STOP Mode Released by RESET Input
  375. CHAPTER 25 RESET FUNCTION
  376. Timing of Reset by RESET Input
  377. Hardware Status after Reset
  378. CHAPTER 26 ROM CORRECTION
  379. Correction Address Registers 0 and 1 Format
  380. ROM Correction Control Registers
  381. ROM Correction Application
  382. Initialization Routine
  383. ROM Correction Operation
  384. ROM Correction Example
  385. Program Execution Flow
  386. Program Transition Diagram (when Two Places are Corrected)
  387. Cautions on ROM Correction
  388. CHAPTER 27 PD78P078, 78P078Y
  389. Internal Memory Size Switching Register
  390. Internal Extension RAM Size Switching Register
  391. PROM Programming
  392. PROM write procedure
  393. Page Program Mode Timing
  394. Byte Program Mode Flowchart
  395. Byte Program Mode Timing
  396. PROM reading procedure
  397. Erasure Procedure ( PD78P078KL-T and 78P078YKL-T Only)
  398. CHAPTER 28 INSTRUCTION SET
  399. Legends Used in Operation List
  400. Description of "operation" column
  401. Operation List
  402. Instructions Listed by Addressing Type
  403. APPENDIX A DIFFERENCES BETWEEN PD78078, 78075B SUBSERIES, AND PD78070A
  404. APPENDIX B DEVELOPMENT TOOLS
  405. B-1 Development Tool Configuration
  406. B.1 Language Processing Software
  407. B.2 PROM Writing Tools
  408. B.3 Debugging Tools
  409. B.3.2 Software
  410. B.5 System Upgrading from Former-type In-circuit Emulator for 78K/0 Series to IE-78001-R-A
  411. B-2 TGC-100SDW Drawing (For Reference Only)
  412. B-3 EV-9200GF-100 Drawing (For Reference Only)
  413. B-4 EV-9200GF-100 Recommended Footprints (For Reference Only)
  414. APPENDIX C EMBEDDED SOFTWARE
  415. APPENDIX D REGISTER INDEX
  416. D.2 Register Symbol Index
  417. APPENDIX E REVISION HISTORY
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This manual is suitable for:
PD78076PD78076YPD78078PD78078YPD78P078PD78P078YuPD78076uPD78076YuPD78078uPD78078YuPD78P078uPD78P078Y
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