CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (μPD78078 SUBSERIES)31817.2 Serial Interface Channel 0 ConfigurationSerial interface channel 0 consists of the following hardware.Table 17-2. Serial Interface Channel 0 ConfigurationItem ConfigurationSerial I/O shift register 0 (SIO0)Slave address register (SVA)Timer clock select register 3 (TCL3)Serial operating mode register 0 (CSIM0)Control register Serial bus interface control register (SBIC)Interrupt timing specify register (SINT)Port mode register 2 (PM2)NoteNote Refer to Figure 6-5 Block Diagram of P20, P21, P23 to P26 and Figure 6-6 BlockDiagram of P22 and P27.Figure 17-2. Serial Interface Channel 0 Block DiagramRemark Output control selects either CMOS output or N-ch open drain output.RegisterCSIE0 COI WUP CSIM04CSIM03CSIM02CSIM01CSIM00Serial OperatingMode Register 0ControlCircuitOutputControlSelectorSI0/SB0/P25 PM25OutputControlSO0/SB1/P26 PM26OutputControlSCK0/P27 PM27SelectorP25OutputLatchP26 OutputLatchCLDP27Output LatchInternal BusBSYE ACKD ACKE ACKT CMDD RELD CMDT RELTInternal BusSlave AddressRegister (SVA)Serial I/O ShiftRegister 0 (SIO0)Bus Release/Command/AcknowledgeDetectorSerial ClockCounterSerial ClockControl CircuitCLRDSETQMatchBusy/AcknowledgeOutput CircuitInterruptRequest SignalGeneratorACKDCMDDRELD WUPSelector SelectorCLD SIC SVAM TCL33 TCL32 TCL31 TCL304CSIM01CSIM00CSIM01CSIM00TO2Interrupt TimingSpecify RegisterTimer Clock SelectRegister 3fxx/2 to fxx /2 8INTCSI0Serial Bus InterfaceControl RegisterSVAM
