410CHAPTER 18 SERIAL INTERFACE CHANNEL 0 (μPD78078Y Subseries)(3) Slave wait release (slave reception)The wait status of a slave is released by setting the WREL flag, which is bit 2 of the interrupt timing specifyregister (SINT), or by executing a serial I/O shift register 0 (SIO0) write instruction.When a slave receives data, if the SCL line immediately enters a high-impedance state due to a write toSIO0, the slave may not receive the first bit of the data sent from the master. This is because SIO0 cannotstart operation if the SCL line is in a high-impedance state during execution of a write instruction to SIO0(until the next instruction execution is started). Therefore, manipulate the P27 output latch through the programas shown in Figure 18-26 to receive data correctly.For these timings, see Figure 18-22.Figure 18-26. Slave Wait Release (Reception)(4) Reception completion of slaveDuring processing of reception completion by a slave device, confirm the statuses of CMDD and COI (ifCMDD = 1). This procedure is necessary to use the wake-up function normally. If an uncertain amount ofdata is sent from the master device, the slave device cannot determine whether the start condition signal orthe data will be sent from the master. This may disable use of the wake-up function.Writingdatato SIO0SettingCSIIF0SettingACKD Serial transmission9 2 3A0 W ACK D7 D6 D5P27outputlatch 1SettingCSIIF0ACKoutput Serial receptionWriteFFHto SIO0P27outputlatch 0WaitreleaseSoftware operationHardware operationSCLSoftware operationHardware operationTransfer lineMaster device operationSlave device operation1SDA0 (SDA1)
