282CHAPTER 12 WATCHDOG TIMER12.4.2 Interval timer operationThe watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an intervalof the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0, respectively.The count clock (interval time) can be selected with bits 0 to 2 (TCL20 to TCL22) of the timer clock select register2 (TCL2). The watchdog timer starts operation as an interval timer when bit 7 (RUN) of WDTM is set to 1.When the watchdog timer operated as interval timer, the interrupt mask flag (TMMK4) and priority specify flag(TMPR4) are validated and the maskable interrupt request (INTWDT) can be generated. Among maskable interruptrequests, the INTWDT default has the highest priority.The interval timer continues operating in the HALT mode but it stops in STOP mode. Thus, set bit 7 (RUN) ofWDTM to 1 before the STOP mode is set, clear the interval timer and then execute the STOP instruction.Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (with the watchdog timer mode selected), the intervaltimer mode is not set unless RESET input is applied.2. The interval time just after setting with WDTM may be shorter than the set time by a maximumof 0.5 %.3. When the subsystem clock is selected for CPU clock, watchdog timer count operation isstopped.Table 12-5. Interval Timer Interval TimeTCL22 TCL21 TCL20 Interval Time MCS = 1 MCS = 00 0 0 2 11 x 1/f XX 2 11 x 1/f X (410μs) 2 12 x 1/f X (819μs)0 0 1 2 12 x 1/f XX 2 12 x 1/f X (819μs) 2 13 x 1/f X (1.64 ms)0 1 0 2 13 x 1/f XX 2 13 x 1/f X (1.64 ms) 2 14 x 1/f X (3.28 ms)0 1 1 2 14 x 1/f XX 2 14 x 1/f X (3.28 ms) 2 15 x 1/f X (6.55 ms)1 0 0 2 15 x 1/f XX 2 15 x 1/f X (6.55 ms) 2 16 x 1/f X (13.1 ms)1 0 1 2 16 x 1/f XX 2 16 x 1/f X (13.1 ms) 2 17 x 1/f X (26.2 ms)1 1 0 2 17 x 1/f XX 2 17 x 1/f X (26.2 ms) 2 18 x 1/f X (52.4 ms)1 1 1 2 19 x 1/f XX 2 19 x 1/f X (104.9 ms) 2 20 x 1/f X (209.7 ms)Remarks 1. f XX : Main system clock frequency (f X or f X /2)2. f X : Main system clock oscillation frequency3. MCS : Bit 0 of oscillation mode selection register (OSMS)4. TCL20 to TCL22 : Bits 0 to 2 of timer clock select register 2 (TCL2)5. Figures in parentheses apply to operation with f X = 5.0 MHz.
