INTERNAL SPECIFICATIONS974.5.3.4 Timer/counter 2 detector circuit4.5.3.4.1 T2 (timer/counter 2 external clock detector)The T2 detector circuit block diagram is shown in Figure 4-23. Operation of this circuit isoutlined below. When the level of the signal applied to T2 (bit 0 of port 1) is changed from “1”to “0”, output of F/Fl becomes “1”. This output signal is then passed to F/F2 at S5 timing andF/F2 output also becomes “1”. The T2 signal change passed to F/F2 is synchronized with theS3 timing signal to become the external clock for timer/counter 2. At the same time, F/F1 isreset and waits for the next external clock input. Note that the “0” and “1” level cycle times ofthe external clock signal applied to the T2 pin must be at least 12 times (12T) the XTAL1·2oscillator clock cycle time T.QDLQDRF/F1 F/F2S5T2[PORT 1.0]V CCRESETTIMER COUNTER 2CLOCK10 12T 12TS3Figure 4-23 Timer/counter 2 external clock detector circuit4.5.3.4.2 T2EX (timer/counter 2 external flag input detector)T2EX detector circuit block diagram is shown in Figure 4-24. Operation of this circuit isoutlined below. When the level of the signal applied to T2EX (bit 1 of port 1) is changed from“1” to “0”, output of F/F1 becomes “1”. This output signal is then passed to F/F2 at S2 timingand F/F2 output also becomes “1”. The T2EX signal change passed to F/F2 Q is synchronizedwith the S4 timing signal to become the T2EX signal for timer/counter 2. At the same time,F/Fl is reset and waits for the next T2EX input. Note that the “0” and “1” level cycle times ofthe external clock signal applied to the T2EX pin must be at least 12 times (12T) the XTAL1·2oscillator clock cycle time T.QDLQDRF/F1 F/F2S2T2EX[PORT 1.0]V CCRESETTIMER COUNTER 2T2EX10 12T 12TS4Figure 4-24 Timer/counter 2 T2EX detector circuit
