Oki MSM85C154HVS User Manual

Also see for MSM80C154S: Specification sheet

Contents

Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
MSM80C154S/MSM83C154S/MSM85C154HVS Outline
MSM80C154S/MSM83C154S Features
Additional Features in MSM80C154S/MSM83C154S/MSM85C154HVS
MSM80C154S/MSM83C154S/MSM85C154HVS Logic Symbols
MSM80C154S/MSM83C154S Pin Layout
system configuration
MSM80C154S/MSM83C154S external dimensions
MSM85C154HVS pin layout and external dimensions
Timing and Control
Major synchronizing signals
MSM80C154S fundamental operation time charts
MOVX A, @DPTR
MOVX @DPTR, A
MSM83C154S fundamental operation time charts
MOV direct, PORT[0, 1, 2, 3] execution
Instruction Register (IR) and Instruction Decoder (PLA)
Arithmetic Operation Section
Program Counter
Program Memory and External Data Memory
Procedures and circuit connections used when external data memory (RAM) is accessed by data pointer (DPTR)
Procedures and circuit connections used when external data memory (RAM) is accessed by registers R0 and R1
Oscillators [XTAL1
CPU Resetting
Reset Schmitt trigger circuit
CPU internal status by reset
EA(CPU Memory Separate)
Internal Data Memory (RAM) and Special Function Registers
Internal Data Memory (RAM)
Internal data memory registers R0 thru R7
Stack
Internal data memory indirect addressing
Internal data memory register R0 thru R7 designation
Internal data memory 1-bit data designation
Special Function Registers(TCON, SCON,...ACC, B)
Special function registers
Power control register (PCON)
Timer control register (TCON)
Serial port control register (SCON)
Interrupt enable register (IE)
Interrupt priority register (IP)
Program status word register (PSW)
I/O control register (IOCON)
Timer 2 control register (T2CON)
Timer/Counters 0, 1, and 2
Timer/counter 0 and 1 count clock designation
External clock detector circuit for timer/counters 0 and 1
Counting control of timer/counters 0 and 1 by INT pin
Timer/counters 0/1 timer modes
Mode 1
Mode 2
Mode 3
bit timer mode
Caution about use of timer counters 0 and 1
Caution about use of timer counters 0 and 1 when setting software power down mode
Timer/counter 2
Timer/counter 2 operation modes
bit capture mode
bit baud rate generator mode
Timer/counter 2 detector circuit
Timer/counter carry signal detector circuit
Serial Port
Special function registers for serial port
SBUF
SMOD
SERR
Operating modes
Outline
Mode 1 transmit operation
Mode 1 UART error detection
Mode 2 baud rate
Mode 2 UART error detection
Mode 3 baud rate
Mode 3 transmit operation
Mode 3 UART error detection
Serial port application examples
Multi-processor systems
Interrupt
Priority interrupt routine flow
Interrupt routine flow when priority circuit is stopped
Interrupt priority when priority register (IP) contents are all "0
Detection of external interrupt signals INT0 and INT1
External interrupt signal 0 and 1 trigger detection
MSM80C154S/MSM83C154S interrupt response time charts
during execution of IE or IP register operation instruction in main routine
executed after temporarily returning to the main routine from continuous interrupt processing
instruction is executed after temporarily returning to the main routine from continuous interrupt processing
CPU "Power Down
Soft power down mode (PD) setting
Hard power down mode (HPD) setting
CPU Power Down Mode (IDLE, PD, and HPD) Cancellation (CPU Activation)
Cancellation of CPU power down mode(IDLE, PD)by interrupt signal
Cancellation of CPU power down mode (IDLE, PD) by interrupt request signal and restart from next address of stop address
MSM80C154S/83C154S Battery Backup with Hard Power Down Mode
PORT
Port 0, 1, 2, and 3 Output and Floating Status Settings in CPU Power Down Mode (PD, HPD)
Port Output Timing
Two machine cycle instruction output timing
Port Data Manipulating Instructions
Absolute Maximum Ratings
DC Characteristics
External Program Memory Access AC Characteristics
External Data Memory Access AC Characteristics
Serial Port (I/O Extension Mode) AC Characteristics
AC Characteristics Measuring Conditions
XTAL1 External Clock Input Waveform Conditions
Description of Instruction Symbols
List of Instructions
Detailed Description of MSM80C154S/MSM83C154S Instructions

DESCRIPTION OF INSTRUCTIONS33980. ORL A, Rr (Logical OR register to accumulator)0 1 0 0 1 r 2 r1 r07 0Instruction codeOperationNumber of bytesNumber of cyclesFlags(PSW)DescriptionExample ORL A, R5Instruction code: Byte 1(A)←(A) OR (Rr) r=0 thru 7:C AC F0 RS1 RS0 OV F1 P•:::The logical OR between the accumulator contents and theregister r contents is determined. The result is placed in theaccumulator and the flag is updated.:0 1 0 0 1 1 0 17 0Byte 1Accumulator0 0 0 0 0 0 0 07 011Before executionAccumulator0 1 1 1 0 1 0 17 0After execution:Register 50 1 1 1 0 1 0 17 0Register 50 1 1 1 0 1 0 17 0

/ 378

Related manuals for Oki MSM80C154S

Oki MSM9225B User Manual

Oki ML60852A Applications Manual

Oki MSM66201 Specification Sheet

This manual is suitable for:

MSM80C154S MSM83C154S MSM85C154HVS MSM8C154S

manualsdatabase

Your AI-powered manual search engine