Oki MSM85C154HVS User Manual Manual pdf 152 page image
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Oki MSM85C154HVS User Manual

Also see for MSM80C154S: Specification sheet

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. MSM80C154S/MSM83C154S/MSM85C154HVS Outline
  7. MSM80C154S/MSM83C154S Features
  8. Additional Features in MSM80C154S/MSM83C154S/MSM85C154HVS
  9. MSM80C154S/MSM83C154S/MSM85C154HVS Logic Symbols
  10. MSM80C154S/MSM83C154S Pin Layout
  11. system configuration
  12. MSM80C154S/MSM83C154S external dimensions
  13. MSM85C154HVS pin layout and external dimensions
  14. Timing and Control
  15. Major synchronizing signals
  16. MSM80C154S fundamental operation time charts
  17. MOVX A, @DPTR
  18. MOVX @DPTR, A
  19. MSM83C154S fundamental operation time charts
  21. MOV direct, PORT[0, 1, 2, 3] execution
  22. Instruction Register (IR) and Instruction Decoder (PLA)
  23. Arithmetic Operation Section
  24. Program Counter
  25. Program Memory and External Data Memory
  26. Procedures and circuit connections used when external data memory (RAM) is accessed by data pointer (DPTR)
  27. Procedures and circuit connections used when external data memory (RAM) is accessed by registers R0 and R1
  28. Oscillators [XTAL1
  29. CPU Resetting
  30. Reset Schmitt trigger circuit
  31. CPU internal status by reset
  32. EA(CPU Memory Separate)
  33. Internal Data Memory (RAM) and Special Function Registers
  34. Internal Data Memory (RAM)
  35. Internal data memory registers R0 thru R7
  36. Stack
  37. Internal data memory indirect addressing
  38. Internal data memory register R0 thru R7 designation
  39. Internal data memory 1-bit data designation
  40. Special Function Registers(TCON, SCON,...ACC, B)
  41. Special function registers
  42. Power control register (PCON)
  43. Timer control register (TCON)
  44. Serial port control register (SCON)
  45. Interrupt enable register (IE)
  46. Interrupt priority register (IP)
  47. Program status word register (PSW)
  48. I/O control register (IOCON)
  49. Timer 2 control register (T2CON)
  50. Timer/Counters 0, 1, and 2
  51. Timer/counter 0 and 1 count clock designation
  52. External clock detector circuit for timer/counters 0 and 1
  53. Counting control of timer/counters 0 and 1 by INT pin
  54. Timer/counters 0/1 timer modes
  55. Mode 1
  56. Mode 2
  57. Mode 3
  58. bit timer mode
  59. Caution about use of timer counters 0 and 1
  60. Caution about use of timer counters 0 and 1 when setting software power down mode
  61. Timer/counter 2
  62. Timer/counter 2 operation modes
  63. bit capture mode
  64. bit baud rate generator mode
  65. Timer/counter 2 detector circuit
  66. Timer/counter carry signal detector circuit
  67. Serial Port
  68. Special function registers for serial port
  69. SBUF
  70. SMOD
  71. SERR
  72. Operating modes
  73. Outline
  74. Mode 1 transmit operation
  75. Mode 1 UART error detection
  76. Mode 2 baud rate
  77. Mode 2 UART error detection
  78. Mode 3 baud rate
  79. Mode 3 transmit operation
  80. Mode 3 UART error detection
  81. Serial port application examples
  82. Multi-processor systems
  83. Interrupt
  86. Priority interrupt routine flow
  87. Interrupt routine flow when priority circuit is stopped
  88. Interrupt priority when priority register (IP) contents are all "0
  89. Detection of external interrupt signals INT0 and INT1
  90. External interrupt signal 0 and 1 trigger detection
  91. MSM80C154S/MSM83C154S interrupt response time charts
  92. during execution of IE or IP register operation instruction in main routine
  93. executed after temporarily returning to the main routine from continuous interrupt processing
  94. instruction is executed after temporarily returning to the main routine from continuous interrupt processing
  95. CPU "Power Down
  96. Soft power down mode (PD) setting
  97. Hard power down mode (HPD) setting
  98. CPU Power Down Mode (IDLE, PD, and HPD) Cancellation (CPU Activation)
  99. Cancellation of CPU power down mode(IDLE, PD)by interrupt signal
  100. Cancellation of CPU power down mode (IDLE, PD) by interrupt request signal and restart from next address of stop address
  101. MSM80C154S/83C154S Battery Backup with Hard Power Down Mode
  102. PORT
  106. Port 0, 1, 2, and 3 Output and Floating Status Settings in CPU Power Down Mode (PD, HPD)
  107. Port Output Timing
  108. Two machine cycle instruction output timing
  109. Port Data Manipulating Instructions
  110. Absolute Maximum Ratings
  111. DC Characteristics
  112. External Program Memory Access AC Characteristics
  113. External Data Memory Access AC Characteristics
  114. Serial Port (I/O Extension Mode) AC Characteristics
  115. AC Characteristics Measuring Conditions
  116. XTAL1 External Clock Input Waveform Conditions
  118. Description of Instruction Symbols
  119. List of Instructions
  120. Detailed Description of MSM80C154S/MSM83C154S Instructions
Oki MSM85C154HVS User Manual Manual pdf 152 page image
INTERNAL SPECIFICATIONS145Figure 4-52 Interrupt response time chart when IE or IP manipulating instruction isexecuted after returning to main routine during continuous interruptprocessingS4 S5 S6 S1 S2 S3XTAL1ALETimer flag 1S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6InstructionexecutionS61 -010 -M2 M1 or M2 M110RETI execution Timer 1 interrput address callExecution of IE or IPmanipulation instruction Execution of one instructionM1~M4M1 or M2
/ 378
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This manual is suitable for:
MSM80C154SMSM83C154SMSM85C154HVSMSM8C154S
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