INTERNAL SPECIFICATIONS634.3.3 Internal data memory 1-bit data designationIn the MSM80C154S/MSM83C154S, 1-bit data manipulations (test, reset, set, complement,transfer) can be executed directly between internal data memory addresses 20 thru 2FH bybit manipulation instructions. The operation of a bit reset instruction is described below as anexample.This instruction (CLR bit address) is a 2-byte 2-machine cycle instruction (see Figure 4-6).The instruction code is indicated in byte 1, and the data memory address and bit designationare indicated in byte 2. The manipulation bit is specified by the b0, b 1, and b 2 data in bits 0,1, and 2 of byte 2. The b 0, b 1, and b 2 portion is expressed in binary code which is weighted1, 2, and 4. Combinations of this code enable any one of eight bits to be specified. The bitdesignation combinations are listed in able 4-4.The data memory is addressed by bits b3 , b 4 , b5 , b 6 and b 7 of byte 2 with b 7 being “0”. Thesebits can be expressed in binary by 0 thru 0FH, and a total of 16 designations of the datamemory are possible.When data memory addresses are specified, the data memory bit manipulation start address20H is added to the b3 , b4 , b 5, and b 6 binary data to obtain the data memory address.The data memory contents specified by the above method are read by the CPU into atemporary register, the specified bit data is reset to “0” by the ALU, and the CPU returns theresult to the data memory where the data were read. One bit of specified data memory is thusreset to “0”.1 1 0 0 0 0 1 07 6 5 4 3 2 1 0Instruction (OP) codeCLR bit address: Byte 1b7 b 6 b5 b4 b3 b2 b1 b07 6 5 4 3 2 1 0Addressdesignation portionBit designationportionByte 2Figure 4-6 CLR bit address bit arrangement
