INTERNAL SPECIFICATIONS614.3 lnternal Data Memory (RAM) Operating Procedures4.3.1 Internal data memory indirect addressingOperation of the internal data memory indirect increment instruction is described here as anexample. This instruction (INC @Rr) is a 1-byte 1-machine cycle instruction (see Figure 4-4). The indirect address register is specified by instruction code bit 0 data r where r denoteseither register 0 or 1 in the register group specified by PSW RS0 and RS1 bank data. Register0 is specified when the r data is 0, and register 1 is specified when the data is 1.When this instruction is executed, register data is read from the specified register 0 or 1, andthe read out register data is written into the data pointer for the data memory.The data memory contents specified by the data pointer are read by the CPU into a temporaryregister. Then a subsequent increment (+1) by the ALU is followed by a return to the datamemory at the address where the data were read out. In this way, the contents of the datamemory at the address specified by the contents of R0 or R1 are incremented.0 0 0 0 0 1 1 r7 6 5 4 3 2 1 0Instruction (OP)code portionRegisterdesignation portionINC @Rr: Byte 1Figure 4-4 INC @Rr bit arrangement
