Oki MSM85C154HVS User Manual Manual pdf 227 page image
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Oki MSM85C154HVS User Manual

Also see for MSM80C154S: Specification sheet

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. MSM80C154S/MSM83C154S/MSM85C154HVS Outline
  7. MSM80C154S/MSM83C154S Features
  8. Additional Features in MSM80C154S/MSM83C154S/MSM85C154HVS
  9. MSM80C154S/MSM83C154S/MSM85C154HVS Logic Symbols
  10. MSM80C154S/MSM83C154S Pin Layout
  11. system configuration
  12. MSM80C154S/MSM83C154S external dimensions
  13. MSM85C154HVS pin layout and external dimensions
  14. Timing and Control
  15. Major synchronizing signals
  16. MSM80C154S fundamental operation time charts
  17. MOVX A, @DPTR
  18. MOVX @DPTR, A
  19. MSM83C154S fundamental operation time charts
  20. MOV direct, PORT[0, 1, 2, 3] execution
  21. Instruction Register (IR) and Instruction Decoder (PLA)
  22. Arithmetic Operation Section
  23. Program Counter
  24. Program Memory and External Data Memory
  25. Procedures and circuit connections used when external data memory (RAM) is accessed by data pointer (DPTR)
  26. Procedures and circuit connections used when external data memory (RAM) is accessed by registers R0 and R1
  27. Oscillators [XTAL1
  28. CPU Resetting
  29. Reset Schmitt trigger circuit
  30. CPU internal status by reset
  31. EA(CPU Memory Separate)
  32. Internal Data Memory (RAM) and Special Function Registers
  33. Internal Data Memory (RAM)
  34. Internal data memory registers R0 thru R7
  35. Stack
  36. Internal data memory indirect addressing
  37. Internal data memory register R0 thru R7 designation
  38. Internal data memory 1-bit data designation
  39. Special Function Registers(TCON, SCON,...ACC, B)
  40. Special function registers
  41. Power control register (PCON)
  42. Timer control register (TCON)
  43. Serial port control register (SCON)
  44. Interrupt enable register (IE)
  45. Interrupt priority register (IP)
  46. Program status word register (PSW)
  47. I/O control register (IOCON)
  48. Timer 2 control register (T2CON)
  49. Timer/Counters 0, 1, and 2
  50. Timer/counter 0 and 1 count clock designation
  51. External clock detector circuit for timer/counters 0 and 1
  52. Counting control of timer/counters 0 and 1 by INT pin
  53. Timer/counters 0/1 timer modes
  54. Mode 1
  55. Mode 2
  56. Mode 3
  57. bit timer mode
  58. Caution about use of timer counters 0 and 1
  59. Caution about use of timer counters 0 and 1 when setting software power down mode
  60. Timer/counter 2
  61. Timer/counter 2 operation modes
  62. bit capture mode
  63. bit baud rate generator mode
  64. Timer/counter 2 detector circuit
  65. Timer/counter carry signal detector circuit
  66. Serial Port
  67. Special function registers for serial port
  68. SBUF
  69. SMOD
  70. SERR
  71. Operating modes
  72. Outline
  73. Mode 1 transmit operation
  74. Mode 1 UART error detection
  75. Mode 2 baud rate
  76. Mode 2 UART error detection
  77. Mode 3 baud rate
  78. Mode 3 transmit operation
  79. Mode 3 UART error detection
  80. Serial port application examples
  81. Multi-processor systems
  82. Interrupt
  83. Priority interrupt routine flow
  84. Interrupt routine flow when priority circuit is stopped
  85. Interrupt priority when priority register (IP) contents are all "0
  86. Detection of external interrupt signals INT0 and INT1
  87. External interrupt signal 0 and 1 trigger detection
  88. MSM80C154S/MSM83C154S interrupt response time charts
  89. during execution of IE or IP register operation instruction in main routine
  90. executed after temporarily returning to the main routine from continuous interrupt processing
  91. instruction is executed after temporarily returning to the main routine from continuous interrupt processing
  92. CPU "Power Down
  93. Soft power down mode (PD) setting
  94. Hard power down mode (HPD) setting
  95. CPU Power Down Mode (IDLE, PD, and HPD) Cancellation (CPU Activation)
  96. Cancellation of CPU power down mode(IDLE, PD)by interrupt signal
  97. Cancellation of CPU power down mode (IDLE, PD) by interrupt request signal and restart from next address of stop address
  98. MSM80C154S/83C154S Battery Backup with Hard Power Down Mode
  99. PORT
  100. Port 0, 1, 2, and 3 Output and Floating Status Settings in CPU Power Down Mode (PD, HPD)
  101. Port Output Timing
  102. Two machine cycle instruction output timing
  103. Port Data Manipulating Instructions
  104. Absolute Maximum Ratings
  105. DC Characteristics
  106. External Program Memory Access AC Characteristics
  107. External Data Memory Access AC Characteristics
  108. Serial Port (I/O Extension Mode) AC Characteristics
  109. AC Characteristics Measuring Conditions
  110. XTAL1 External Clock Input Waveform Conditions
  111. Description of Instruction Symbols
  112. List of Instructions
  113. Detailed Description of MSM80C154S/MSM83C154S Instructions
/ 378
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This manual is suitable for:
MSM80C154SMSM83C154SMSM85C154HVSMSM8C154S
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