MSM80C154S/83C154S/85C154HVS302.7 Instruction Register (IR) and Instruction Decoder (PLA)MSM80C154S/MSM83C154S operations are based on an instruction code address method.Hence, in addition to the instruction code instruction register (IR) and instruction decoder(PLA), these devices also include an instruction register (AIR) and register manipulationdecoder (PLA) for data addresses and bit addresses.Operation codes are passed to the IR, and data and bit addresses are passed to the AIR. CPUcontrol signals are formed at the respective PLA for each instruction register, therebyactivating the CPU. The block diagram is outlined in Figure 2-21.MatrixDecoderAIRData busWAIRAND Control signalsTimingPLAMatrixDecoderIRData busWIRControl signalsTimingPLAANDFigure 2-21 lR and PLA block diagram
