41309401TH Rev.4 310 /Data/Address BusM D-motorPrinter controlOST-EXBuffer 640 bytesDecoding(RLE,TIFF,ACC32)200-300 convertersmoothingVarious Sensor2/41/4LED head300 dpiData/Address Bus High-voltageController4/4High-voltagePower SupplyData/Address Bus Peripheral control1284 controlCS generationI/O portDMA 2ch3/4Bi-CentroI/FOPE unitSpeaker+5V IC1X120 MHzCLK20 MHzInitial Reset CircuitPOWRDY(CPU: SH7034)XTALEXTALAddress BusData/Address busCLKClutchFigure A.6 Related Signals of IOGA43. 46F Circuit Diagram (OKIFAX4550)3.1 46F Circuit Diagram (1/13)1. Block diagram46F-PCB circuit diagram (1/13) shown the consists of an input/output gate array IC2 (IOGA4),crystal oscillator circuit and reset signal generator.Figure A.6 shown the block diagram of IC2 (IOGA4) and the peripheral circuits.2. Function1) IOGA4 is newly developed LSI for scanning, printing control and provided with a built-inCPU.- IOGA4 contains the following functions:• Scanned data DMA control• Strobe signals control for LED head• Smoothing control for printing data• Interface of the peripheral LSI- CPUCPU controls the following functions in addition to the basic processor.• DMA (Direct Memory Access) control• Interrupt procedure control• A/D converter• Bus state control• Programmable pattern control• 16 bit integrated timer pulse unit (ITU)• Timing pattern control (TPC)• Serial communication interface (SCT)2) Crystal oscillator circuitX1 is 20MHz crystal oscillator. The output wave is fed to the IOGA4 (CPU) through pin 14and 15. CLK (20MHz) signal output from pin 94 is used as the system clock.
