Timers16-Bit Timer Setup ExamplesPanasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual108Panasonic4.11.5 Setting Up a Two-Phase Capture Input Using Timer 4In this example, timer 4 is used to divide the timer 0 underflow by 65,536 andmeasure the number of cycles from the rising edge of the TM4IA input signal tothe rising edge of the TM4IB input signal. An interrupt occurs on capture B andthe software calculates the number of cycles by subtracting the contents ofTMnCA from the contents of TMnCB.n To set up timer 0:1. Disable timer 0 counting in the timer 0 mode register (TM0MD). This step isunnecessary immediately after a reset, since TM0MD resets to 0.TM0MD (example) x’00FE20’2. Set the divide-by ratio for timer 0. To divide B OSC /4 by two, write x’01’ tothe timer 0 base register (TM0BR). (The valid range for TM0BR is 0 to255.)A. Chip LevelB. Block LevelFigure 4-37 Block Diagram of Two-Phase Capture Input Using Timer 4TM4IATM4IBP3P6P4P5COREInterruptsTimers 0-3Timers 4-5ROM, RAMBus ControllerSerial I/FsADCP2TM4IAInterrupt BTimer 0underflowupTM4BCTimer 4TM4CATM4CBTM4IBT QT QRS QControllerBit: 7 6 5 4 3 2 1 0TM0ENTM0LD — — — — TM0S1TM0S0Setting: 0 0 0 0 0 0 — —
