On-Screen DisplayDMA and Interrupt TimingMN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company191Panasonic7.11 DMA and Interrupt TimingThis section describes how the MN102H75K/85K handles the timing of directmemory access (DMA) transfers of OSD data and OSD interrupts.n DMAIf you use the OSD function, theDMA function executes for boththe text and graphics layers,even if your program does notuse one of these layers. Toprevent error, program data forthe unused layer to meet therestrictions outlined in section7.1, “Description,” on page 153.On both the text and graphics layers, the microcontroller reads the line 1 datafrom the RAM as it scans line 1 onto the display. For line 2 and following lines, itreads the data as it scans the display start for the preceding line. The RAM readstarts 12 system clock cycles (12T S ) after the leading edge of the HSYNC pulse.The DMA transfer takes 4T S for each display data word.In line 1, or when a graphics and text line begin simultaneously, the data transferrequests for both layers occur simultaneously. The text data transfer always takespriority. The graphics data transfer begins 5TS after the text data transfer ends.If a DMA transfer occurs at the same time as the leading edge of a VSYNC pulse,the screen flickers. To avoid this, do not set a display position in the last line.InterruptsFor both graphics and text displays, the microcontroller processes the GINT andCINT interrupt request bits of the display data’s GVP and CVP fields duringDMA transfer. If GINT or CINT is set to 1, when the associated transfer ends(GVP or CVP transfer) the OSD generates an interrupt request.Note that if the interrupt bit is set to 1 in the line 1 display data, the interruptoccurs at the first scan line. If the interrupt bit is set to 1 in the line 2 display data,the interrupt occurs at the first display line.n
