General DescriptionMN102H Series OverviewPanasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual18Panasonic1 General Description1.1 MN102H Series OverviewThe 16-bit MN102H series is the high-speed linear addressing version of theMN10200 series. The new architecture in this series is designed for C-languageprogramming and is based on a detailed analysis of the requirements forembedded applications. From miniaturization to power savings, it provides for awide range of needs in user systems, surpassing all previous architectures inspeed and functionality.This series uses a load/store architecture for computing within the registers ratherthan the accumulator system for computing within the memory space, whichPanasonic has used in most of its previous major series. The basic instructionsare one byte/one machine cycle, drastically shrinking code size and improvingcompiler efficiency. The circuit is designed for submicron technology, providingoptimized hardware and low system power consumption.The devices in this series contain up to 16 megabytes of linear address space andenable highly efficient program development. In addition, the optimizedhardware structure allows for low system-wide power consumption even in largesystems.1.2 MN102H Series FeaturesDesigned for embedded applications, the MN102H series contains a flexible andoptimized hardware architecture as well as a simple and efficient instruction set.It provides both economy and speed. This section provides the features of theMN102H series CPU.n High-speed signal processingAn internal multiplier multiplies two 16-bit registers for a 32-bit product in asingle cycle. In addition, the hardware contains a saturation calculator toensure that no signal processing is missed and to increase signal processingspeed.n Linear addressing for large systemsThe MN102H series provides up to 16 megabytes of linear address space.With linear addressing, the CPU does not detect any borders betweenmemory banks, which provides an effective development environment. Thehardware architecture is also optimized for large-scale designs. The memoryis not divided into instruction and data areas, so operations can shareinstructions.
