General DescriptionMN102H Series FeaturesMN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company19Panasonicn Single-byte basic instruction lengthThe MN102H series has replaced general registers with eight internal CPUregisters divided functionally into four address registers (A0 - A3) and fourdata registers (D0 - D3). The program can address a register pair in four orless bits, and basic instructions such as register-to-register operations andload/store operations occupy only one byte.n High-speed pipeline throughputThe MN102H series executes instructions in a high-speed three-stagepipeline: fetch, decode, execute. With this architecture, the MN102H seriescan execute single-byte instructions in only one machine cycle (50 ns at 40MHz).n Simple instruction setThe MN102H series uses a streamlined set of 41 instructions, designed spe-cifically for the programming model for embedded applications. To shrinkcode size, instructions have a variable length of one to seven bytes, and themost frequently used basic instructions are single-byte.Figure 1-1 Conventional vs. MN102H Series Code AssignmentsFigure 1-2 Three-Stage Pipeline7 6 5 4 3 2 1 0Register specification(An/Dn)Conventional code assignment for general register instructionsNew Panasonic code assignments15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Register specification(GRn)1 machine cycleTimeInstruction 1 Fetch DecodeAddresscalculationFetchExecuteDecodeAddresscalculation ExecuteInstruction 2
