Timers16-Bit Timer Setup ExamplesMN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company95PanasonicTM4CA (example) x’00FE84’3. Set the phase difference for timer 4. For a 2-cycle phase difference, writex’0001’ to timer 4 compare/capture register B (TM4CB). (The valid range is-1 ≤ TM4CB < the TM4CA value.)TM4CB (example) x’00FE88’4. Set the TM4NLD bit of the TM4MD register to 1 and the TM4EN bit to 0.This enables TM4BC and the S-R flip-flop. This step ensures stable opera-tion. If it is omitted, the binary counter may not count the first cycle. Do notchange any other operating modes during this step.5. Set TM4NLD and TM4EN to 1. This starts the timer. Counting begins at thestart of the next cycle.n To enable timer 4 capture interrupts:Cancel all existing interrupt requests. Next, set the interrupt priority level in theTM4CBLV[2:0] bits of the TM4CBICH register (levels 0 to 6), set the TM4CBIEbit to 1, set the TM4CBIR bit of TM4CBICL to 0, set the TM4CAIE bit ofTM4CAICH to 1, and set the TM4CAIR bit of TM4CAICL to 0. From this pointon, an interrupt request is generated whenever a timer 4 capture A or capture Bevent occurs.Timer 4 can operate as an event counter, but timer 4 does not operate in STOPmode, when B OSC is off. If you use an external clock, it must be synchronized toBOSC. This means that the frequency of the event counter clock must be 1/4 orless that of the oscillator (6 MHz with a 24-MHz oscillator).Figure 4-28 shows an example timing chart.Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0TM4CA15TM4CA14TM4CA13TM4CA12TM4CA11TM4CA10TM4CA9TM4CA8TM4CA7TM4CA6TM4CA5TM4CA4TM4CA3TM4CA2TM4CA1TM4CA0Setting: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0TM4CB15TM4CB14TM4CB13TM4CB12TM4CB11TM4CB10TM4CB9TM4CB8TM4CB7TM4CB6TM4CB5TM4CB4TM4CB3TM4CB2TM4CB1TM4CB0Setting: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1Figure 4-28 Event Counter Timing (Timer 4)TM4CATM4CBTM4BCTM4IBInterruptsB0000 0003 00000001000400010002 0004 00030001 0002 0004BA A
