General DescriptionGeneral SpecificationsPanasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual26Panasonic1.4 General SpecificationsTable 1-1 General SpecificationsParameter SpecificationStructure Internal multiplier (16-bit × 16-bit = 32-bit) and saturate calculatorLoad/store architectureEight registers:© Four 24-bit data registers© Four 24-bit address registersOther:© 24-bit program counter© 16-bit processor status word© 16-bit multiply/divide registerInstruction set © 41 instructions© 6 addressing modes© 1-byte basic instruction length© Code assignment: 1 byte (basic) + 0 to 6 bytes (extension)Performance 12-MHz internal operating frequency (with a 4-MHz external oscilla-tor)Instruction execution clock cycles:© Minimum 1 clock cycle (83.3 ns) for register-to-register operations© Minimum 1 clock cycle (83.3 ns) for load/store operations© Minimum 2 clock cycles (167 ns) for branch operationsPipeline 3-stage: fetch, decode, executeAddress space © Linear address space© Shared instruction/data spaceInterrupts © 6 external© 30 internal© 7 priority level settingsLow-power modes © STOP© HALT© SLOWOscillation fre-quency4 MHz (48 MHz with internal PLL)
