I 2 C Bus ControllerI 2 C Bus Interface RegistersPanasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual304Panasonic13.7 I 2 C Bus Interface RegistersAll registers in I2 C blook cannot be written by byte (by word only). Read by byteis possible.I2CDTRM: I 2 C Transmission Data Register x’007E40’SCL is held low during interruptservicing, and is cleared high bya write to I2CDTRM.STA: I 2C start controlSTO: I2C stop controlWriting to the STA and STO bits allows you to change the state of thetransmission or reception operation. Table 13-6 shows the settings for dif-ferent start and stop conditions.ACK: Acknowledge signal output controlThe acknowledge signal is output after every byte transfer, on the ninthclock pulse. ACK is normally 1 and transitions to 0 to output an acknowl-edge (for instance if the master or slave receiver has received a data byte).DT[7:0]: Data to be transmittedThe parallel data in this field is converted to serial data for transmission tothe I 2 C bus. It is shifted out MSB first to the interface.Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0— — — — — STA STO ACK DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WTable 13-6 STA and STO SettingsSTA STO Mode Function Description0 0 All NOP No state change1 1 All NOP No state change1 0 Slave receiver Start Change to mode indicated by R/W bit.R/W = 0: Change to master transmitterR/W = 1: Change to master receiverMaster transmitter Repeat start0 1 Slave receiver Stop read Change to slave receiver after stopcondition.Master transmitter Stop write
