TB8100 Service Manual Reciter Circuit Description 29© Tait Electronics Limited September 20062.1 Digital CircuitryRefer to Figure 2.2 on page 31.2.1.1 Digital IFVHF Reciter The heart of the digital IF system is the 14-bit analogue-to-digital converter(ADC). This is a high-speed device, with a multi-staged “pipeline”architecture, which is clocked and outputs samples at 40MSPS(megasamples per second). The analogue IF input of the ADC is adifferential structure, and the output is via a 14-bit parallel bus.The band-limited 16.9MHz IF signal is sampled by the ADC at 40MSPS.The sampling process results in images of the input signal appearing at otherfrequencies so that the ADC behaves in a similar fashion to a mixer. Thedigital output therefore contains the wanted signal and the images, whichcan be digitally processed to extract one of the many signals. The desired IFis at 16.9MHz.The digital downconverter (DDC) digitally downconverts the 16.9MHz IFto baseband. This is achieved by digital mixing with a numericallycontrolled oscillator (NCO). The mixing process is done using in-phase andquadrature methods to achieve image rejection, and allows channel filteringto be applied before the signal is passed to the digital signal processor (DSP)for demodulation. The digital channel filtering also decimates the samplerate down to 50kSPS (kilosamples per second) for the DSP.UHF Reciter The heart of the digital IF system is the 14-bit analogue-to-digital converter(ADC). This is a high-speed device, with a multi-staged “pipeline”architecture, which is clocked and outputs samples at 40MSPS(megasamples per second). The analogue IF input of the ADC is adifferential structure, and the output is via a 14-bit parallel bus.The band-limited 70.1MHz IF signal is sub-sampled by the ADC at40MSPS. The sub-sampling results in images of the input signal appearingat other frequencies so that the ADC behaves in a similar fashion to a mixer.The digital output therefore contains information in the form of images,which can be digitally processed to extract one of the many signals. Thelowest frequency image for the 70.1MHz IF and 40MHz clock is at9.9MHz.The digital downconverter (DDC) digitally downconverts the desired image(9.9MHz) to baseband. This is achieved by digital mixing with anumerically controlled oscillator (NCO). The mixing process is done usingin-phase and quadrature methods to achieve image rejection, and allowschannel filtering to be applied before the signal is passed to the digital signalprocessor (DSP) for demodulation. The digital channel filtering alsodecimates the sample rate down to 50kSPS (kilosamples per second) for theDSP.
