TB8100 Service Manual Reciter Circuit Description 39© Tait Electronics Limited September 2006wide bandwidth. The appropriate filter is selected by software-controlledPIN switches, according to the bandwidth selected in the Service Kit(Configure > Base Station > Channel Profiles > General tab).The IF amplifier is a two-transistor design with voltage and currentfeedback, which provides sufficient gain to drive the digital receiver. The16.9MHz signal is finally passed to the analogue-to-digital converter (ADC)in the digital receiver via an anti-alias filter. This filter prevents IF noise atfrequencies above 16.9MHz, generated in the amplifier, from being sampledby the ADC at other Nyquist zones.2.3.4 SynthesizerThe receiver synthesizer consists of a programmable frequency synthesizerIC, the receiver VCO, and a stable known reference.The synthesizer uses a phase-locked loop to lock the receiver VCO to astable known frequency reference. The synthesizer IC receives the dividerand control information from the RISC processor via a 3-wire serial bus(clock, data and enable). When the data bits are latched in, the synthesizerprocesses the incoming signals from the VCO feedback signal (fvcofb) andthe reference oscillator (f ref ).The VCO feedback attenuator is a resistive divider that terminates the VCOfeedback signal in a fixed low impedance (50Ω). This attenuates the VCORF level down to a level suitable for the RF prescaler (within the synthesizerIC).A 12.8MHz temperature controlled crystal oscillator (TCXO) is used as theinternal reference oscillator. When the TCXO is active, the receiversynthesizer is locked to an “internal reference mode” (by default).Alternatively, a phase-locked 12.8MHz voltage controlled crystal oscillator(VCXO) can be used as the external reference oscillator. When the VCXOis active, the receiver synthesizer is locked to an “external reference mode”.In operation only one oscillator is active at any given time. Refer to“Reference Switch” on page 35 for details on the phase-locked 12.8MHzexternal reference oscillator.The reference oscillators are buffered, branched, and divided down to the3.125kHz (default) or 2.5kHz divider reference within the synthesizer IC.The same divider reference is maintained by dividing the VCO feedbacksignal using the prescaler and programmable dividers of the synthesizer IC.Phase lock is achieved when both divider references have the same phase andfrequency content (i.e. their difference is zero or DC). This is achieved bythe phase detector (part of the synthesizer IC), which compares both dividerreferences and delivers an error signal. A ±4mA charge pump circuit (alsopart of the synthesizer IC) and the active loop filter circuit convert this errorsignal to a DC voltage (0 to 22V 1 ) to tune the VCO for correction. The1. The normal lock range is between 3V and 16V.