Panasonic MN102F85K manuals
MN102F85K
Table of contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- About This Manual
- Related Documents
- General Description
- Conventional vs. MN102H Series Code Assignments
- MN102H Series Interrupt Servicing
- MN102H Series Description
- Internal Registers, Memory, and Special Function Registers
- Address Space
- Interrupt Controller Configuration
- General Specifications
- Block Diagram
- Block Diagram Explanation
- Pin Descriptions
- MN102H75K Pin Description
- Pin Functions
- Power Supply Wiring
- Bus Interface
- Bus Interface Control Registers
- Interrupts
- Interrupt Vector Group and Class Assignments
- Handler Preprocessing
- Interrupt Setup Examples
- Timing for External Pin Interrupt Setup (Example)
- Setting Up a Watchdog Timer Interrupt
- Timing for Watchdog Timer Interrupt Setup (Example)
- Interrupt Control Registers
- Panasonic
- Low-Power Modes
- Exiting from SLOW Mode to NORMAL Mode
- Notes on Invoking and Exiting STOP and HALT Modes
- Turning Individual Functions On and Off
- CPU Control Register
- Timers
- Bit Timer Features
- Bit Timer Block Diagrams
- Timer 2 Block Diagram
- Bit Timer Timing
- Bit Timer Setup Examples
- Event Counter Timing (Timer 0)
- Setting Up an Interval Timer Using Timers 1 and 2
- Interval Timer Timing (Timers 1 and 2)
- Bit Timer Control Registers
- Bit Timer Description
- Bit Timer Functions and Features
- Timer 4 Block Diagram
- Single-Phase PWM Output Timing with Data Change (16-Bit Timers)
- External Count Direction Control Timing (16-Bit Timers)
- Two-Phase Capture Input Timing (16-Bit Timers)
- Setting Up an Event Counter Using Timer 4
- Event Counter Timing (Timer 4)
- Setting Up a Single-Phase PWM Output Signal Using Timer 4
- Single-Phase PWM Output Timing (Timer 4)
- Setting Up a Two-Phase PWM Output Signal Using Timer 4
- Two-Phase PWM Output Timing (Timer 4)
- Setting Up a Single-Phase Capture Input Using Timer 4
- Single-Phase Capture Input Timing (Timer 4)
- Setting Up a Two-Phase Capture Input Using Timer 4
- Two-Phase Capture Input Timing (Timer 4)
- Setting Up a 4x Two-Phase Encoder Input Using Timer 5
- Count Direction for 4x Two-Phase Encoder Timing Example
- Setting Up a 1x Two-Phase Encoder Input Using Timer 5
- Count Direction for 1x Two-Phase Encoder Timing Example
- Setting Up a One-Shot Pulse Output Using Timer 5
- One-Shot Pulse Output Timing (Timer 5)
- Setting Up an External Count Direction Controller Using Timer 5
- External Count Direction Control Timing (Timer 5)
- Setting Up External Reset Control Using Timer 5
- External Reset Control Timing (Timer 5)
- Serial Interfaces
- Connecting the Serial Interfaces
- UART Mode Baud Rates
- UART Mode Timing
- Serial Interface Setup Examples
- UART Transmission Timing (Serial Interface 0)
- Setting Up Synchronous Serial Reception Using Serial Interface 0
- Setting Up the Serial Interface Clock
- Serial Interface Clock Timing
- Serial Interface Control Registers
- Analog-to-Digital Converter
- A/D Conversion Timing
- Single Channel/Single Conversion Timing
- Single Channel/Continuous Conversion Timing
- ADC Setup Examples
- Setting Up Hardware-Controlled Intermittent Three-Channel A/D Conversion
- ADC Control Registers
- Caution about Analog-to-Digital Converter
- On-Screen Display
- Power-Saving Considerations in the OSD Block
- OSD Operation
- Output Pin Setup
- Conditions for VRAM Writes
- Standard and Extended Display Modes
- Graphics Layer Display Modes
- Display Setup Examples
- Graphics Display Example
- Setting Up the Text Layer
- Text Display Example
- VRAM
- VRAM Organization
- Graphics VRAM Organization for Two Modes
- Cautions about the number of display code set to VRAM
- ROM Organization
- Graphics ROM Organization in Different Color Modes
- Graphics ROM in the Four Color Modes (16W x 16H Tiles)
- Graphics ROM in the Four Color Modes (16W x 18H Tiles)
- Graphics ROM Organization in 16-Color Mode (16W x 16H Tiles)
- Graphics ROM Organization in 16-Color Mode (16W x 18H Tiles)
- Setting Up the OSD
- RGB, YM, and YS Output Control Settings
- OSD Signal Waveform
- OSD Signal Output Switches
- Text Layer Functions
- Box Shadowing Example
- Italicizing and Underlining Example
- Display Sizes
- Character Size Combinations
- Setting Up the OSD Display Position
- DMA and Interrupt Timing
- DMA and Interrupt Timing for the OSD
- Selecting the OSD Dot Clock
- Controlling the Shuttering Effect
- Shuttered Area Setup Examples
- Controlling Shutter Movement
- Shutter Movement Setup Examples
- Controlling Shuttering Effects
- Text-Layer Shuttering Setup Examples
- Controlling Line Shuttering
- Field Detection Circuit
- Considerations for Interlaced Displays
- OSD Registers
- Cursor Vertical Size Settings
- Graphics Vertical Size Settings
- Text Vertical Size Settings
- IR Remote Signal Receiver
- MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company
- IR Remote Signal Receiver Operation
- Bit Data Reception
- Identifying the Data Format
- Generating Interrupts
- Controlling the SLOW Mode
- IR Remote Signal Receiver Control Registers
- Closed-Caption Decoder
- Functional Description
- Clamping Circuit
- Sync Separator Circuit
- HSYNC Separator
- VSYNC Separator
- Controller and Sampling Circuit
- CRI Detection for Sampling Clock Generation
- Closed-Caption Decoder Registers
- SLSF and SLHD Multiplexing
- Backporch Position Setting
- BSP and PSP Multiplexing
- Pulse Width Modulator
- PWM Data Registers
- I/O Ports
- I/O Port Circuit Diagrams
- P03/ADIN0 to P07/ADIN4 (Port 0)
- P10/ADIN5/IRQ1, P11/ADIN6/IRQ2, and P12/ADIN7/IRQ3 (Port 1)
- P13/ADIN8/WDOUT and P14/ADIN9/STOP (Port 1)
- P15/ADIN10/PWM0 and P16/ADIN11/PWM1 (Port 1)
- PWM2 (Port 1), P20/PWM3, P21/PWM4, P22/PWM5, and P23/PWM6 (Port 2)
- P24/TM4IC/SBT1 (Port 2)
- P27/TM0IO (Port 2)
- P35/DAROUT/R, P36/DAGOUT/G, P37/DABOUT/B (Port 3), and P40/DAYMOUT/YM (Port 4)
- P25/TM4IOB/SBI1/SBD1 and P26/TM4IOA/SBO1 (Port 2)
- P55 and P56 (Port 5)
- P57/SBT0 (Port 5)
- P02/SCL1 (Port 0) and P61/SCL0 (Port 6)
- P01/SDA1 (Port 1) and P60/SDA0 (Port 6)
- P31/CVBS0 and P32/CVBS1 (Port 3)
- P30/CLH and P33/CLL (Port 3)
- P34/VREF (Port 3)
- P41/TM1IO, P42/TM5IOA, and P43/TM5IOB/HI0 (Port 4)
- P45/OSDXO and P46/OSDXI (Port 4)
- P47/HSYNC (Port 4)
- P50/SYSCLK (Port 5)
- P51/YS (Port 5)
- P52/IRQ4/VI0 (Port 5)
- P53/RST (Port 5)
- P54/IRQ5/VSYNC (Port 5)
- I/O Port Control Registers
- ROM Correction
- Programming Considerations
- ROM Correction Control Registers
- Description
- Control Registers for Clamping Circuit
- Setting Up the I 2 C Bus Connection
- SDA and SCL Waveform Characteristics
- Pre-configuring
- Setting Up the Second Interrupt
- Setting Up a Transition from Slave Receiver to Slave Transmitter
- Setting Up the Third Interrupt
- STA and STO Settings
- H Counter
- H Counter Pins
- H Counter Control Registers
- Appendix A Register Map
- A-2 Register Map: x'00FC00' to x'00FDFF
- A-3 Register Map: x'00FE00' to x'00FFFF
- B.1 Description
- B.2 Benefits
- B-2 PROM Writer Hardware
- B.4 Using the Onboard Serial Programming Mode
- B.4.1 Configuring the System for Onboard Serial Programming
- B.4.2 Circuit Requirements for the Target Board
- B.4.3 Microcontroller Hardware Used in Onboard Serial Programming
- B.4.4 Microcontroller Memory Map Used During Onboard Serial Programming
- B.4.4.2 RAM Address Space
- B.4.6 Setting Up the Onboard Serial Programming Mode
- B-9 Load Program Start Flow
- B.4.7 Branching to the User Program
- B.5 Reprogramming Flow
- Questions and Comments
manualsdatabase
Your AI-powered manual search engine