NEC PD78P078Y manuals
PD78P078Y
Table of contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Features
- Application Fields
- Quality Grade
- Pin Configuration (Top View)
- K/0 Series Expansion
- Block Diagram
- Outline of Function
- Mask Options
- CHAPTER 2 OUTLINE ( PD78078Y SUBSERIES)
- Ordering Information
- Differences with PD78054Y Subseries
- Pin Function List
- PROM programming mode pins ( PD78P078 only)
- Description of Pin Functions
- P20 to P27 (Port 2)
- P30 to P37 (Port 3)
- P50 to P57 (Port 5)
- P70 to P72 (Port 7)
- P90 to P96 (Port 9)
- P130 and P131 (Port 13)
- IC (Mask ROM version only)
- Input/output Circuits and Recommended Connection of Unused Pins
- List of Pin Input/Output Circuits
- CHAPTER 4 PIN FUNCTION ( PD78078Y SUBSERIES)
- PROM programming mode pins ( PD78P078Y only)
- P00 to P07 (Port 0)
- P40 to P47 (Port 4)
- P60 to P67 (Port 6)
- P80 to P87 (Port 8)
- P100 to P103 (Port 10)
- AV REF0
- Pin Input/Output Circuit Types
- Memory Spaces
- Memory Map ( PD78078, 78078Y)
- Memory Map ( PD78P078, PD78P078Y)
- Internal program memory space
- Vector Table
- Internal data memory space
- Data memory addressing
- Data Memory Addressing ( PD78078, 78078Y)
- Data Memory Addressing ( PD78P078, 78P078Y)
- Processor Registers
- Stack Pointer Configuration
- General registers
- Special function register (SFR)
- Special Function Register List
- Instruction Address Addressing
- Immediate addressing
- Table indirect addressing
- Register addressing
- Operand Address Addressing
- Direct addressing
- Short direct addressing
- Special function register (SFR) addressing
- Register indirect addressing
- Based addressing
- Based indexed addressing
- Port Functions
- Port Functions ( PD78078 Subseries)
- Port Functions ( PD78078Y Subseries)
- Port Configuration
- Block Diagram of P00 and P07
- Port 1
- Port 2 ( PD78078 Subseries)
- Block Diagram of P22 and P27
- Port 2 ( PD78078Y Subseries)
- Port 3
- Port 4
- Port 5
- Port 6
- Block Diagram of P60 to P63
- Port 7
- Block Diagram of P71 and P72
- Port 8
- Port 9
- Block Diagram of P90 to P93
- Port 10
- Block Diagram of P102 and P103
- Port 12
- Port 13
- Port Function Control Registers
- Port Mode Register and Output Latch Settings when Using Alternate Function
- Port Mode Register Format
- Pull-Up Resistor Option Register Format
- Memory Expansion Mode Register Format
- Key Return Mode Register Format
- Port Function Operations
- Selection of Mask Option
- Clock Generator Functions
- Clock Generator Configuration
- Clock Generator Control Register
- Processor Clock Control Register Format
- Relationship between CPU Clock and Minimum Instruction Execution Time
- Oscillation Mode Selection Register Format
- System Clock Oscillator
- Subsystem clock oscillator
- Divider
- Clock Generator Operations
- Main system clock operations
- Subsystem clock operations
- Changing System Clock and CPU Clock Settings
- System clock and CPU clock switching procedure
- Outline of Timers Incorporated into PD78078, 78078Y Subseries
- Timer/Event Counter Operations
- Bit Timer/Event Counter Functions
- Bit Timer/Event Counter Square-Wave Output Ranges
- Bit Timer/Event Counter Configuration
- Bit Timer/Event Counter Block Diagram
- Bit Timer/Event Counter Output Control Circuit Block Diagram
- INTP0/TI00 Pin Valid Edge and CR00 Capture Trigger Valid Edge
- Bit Timer/Event Counter Control Registers
- Timer Clock Selection Register 0 Format
- Bit Timer Mode Control Register Format
- Capture/Compare Control Register 0 Format
- Bit Timer Output Control Register Format
- Port Mode Register 3 Format
- External Interrupt Mode Register 0 Format
- Sampling Clock Select Register Format
- Bit Timer/Event Counter Operations
- Interval Timer Configuration Diagram
- PWM output operations
- Control Register Settings for PWM Output Operation
- Example of D/A Converter Configuration with PWM Output
- PPG output operations
- Pulse width measurement operations
- Configuration Diagram for Pulse Width Measurement by Free-Running Counter
- Control Register Settings for Two Pulse Width Measurements with Free-Running Counter
- Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified)
- Control Register Settings for Pulse Width Measurement by Means of Restart
- External event counter operation
- External Event Counter Configuration Diagram
- Square-wave output operation
- Square-Wave Output Operation Timing
- One-shot pulse output operation
- Timing of One-Shot Pulse Output Operation Using Software Trigger
- Control Register Settings for One-Shot Pulse Output Operation Using External Trigger
- Bit Timer/Event Counter Operating Precautions
- Capture Register Data Retention Timing
- Operation Timing of OVF0 Flag
- Bit Timer/Event Counters 1 and 2 Functions
- Bit Timer/Event Counters 1 and 2 Interval Times
- Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges
- bit timer/event counter mode
- Square-Wave Output Ranges when 8-Bit Timer/Event Counters 1 and 2 are Used as 16-Bit Timer/Event Counters
- Bit Timer/Event Counters 1 and 2 Configurations
- Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1
- Bit Timer/Event Counters 1 and 2 Control Registers
- Timer Clock Select Register 1 Format
- Bit Timer Mode Control Register 1 Format
- Bit Timer/Event Counters 1 and 2 Operations
- Bit Timer/Event Counter 1 Interval Time
- Bit Timer/Event Counter 2 Interval Time
- External Event Counter Operation Timings (with Rising Edge Specified)
- Timing of Square Wave Output Operation
- Interval Timer Operation Timing
- are Used as 16-Bit Timer/Event Counter
- Square-Wave Output Ranges when 2-Channel 8-Bit Timer/Event Counters TM1 and TM2) are Used as 16-Bit Timer/Event Counter
- Bit Timer/Event Counters 1 and 2 Precautions
- Timing after Compare Register Change during Timer Count Operation
- CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6
- Bit Timer/Event Counters 5 and 6 Interval Times
- Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges
- Bit Timer/Event Counters 5 and 6 Configurations
- Block Diagram of 8-Bit Timer/Event Counters 5 and 6 Output Control Circuit
- Bit Timer/Event Counters 5 and 6 Control Registers
- Timer Clock Select Register 6 Format
- Bit Timer Output Control Register 6 Format
- Port Mode Register 10 Format
- Bit Timer/Event Counters 5 and 6 Operations
- Bit Timer Mode Control Register Setting for External Event Counter Operation
- Square-wave output
- Bit Timer Control Register Settings for PWM Output Operation
- PWM Output Operation Timing (Active High Setting)
- PWM Output Operation Timings (CRn0 = FFH, Active High Setting)
- Bit Timer/Event Counters 5 and 6 Precautions
- Timings after Compare Register Change during Timer Count Operation
- CHAPTER 11 WATCH TIMER
- Watch Timer Configuration
- Watch Timer Control Registers
- Timer Clock Select Register 2 Format
- Watch Timer Mode Control Register Format
- Watch Timer Operations
- CHAPTER 12 WATCHDOG TIMER
- Interval Times
- Watchdog Timer Configuration
- Watchdog Timer Control Registers
- Watchdog Timer Mode Register Format
- Watchdog Timer Operations
- Interval timer operation
- CHAPTER 13 CLOCK OUTPUT CONTROL CIRCUIT
- Clock Output Control Circuit Configuration
- Clock Output Function Control Registers
- Timer Clock Select Register 0 Format
- CHAPTER 14 BUZZER OUTPUT CONTROL CIRCUIT
- Buzzer Output Function Control Registers
- CHAPTER 15 A/D CONVERTER
- A/D Converter Block Diagram
- A/D Converter Control Registers
- A/D Converter Mode Register Format
- A/D Converter Input Select Register Format
- External Interrupt Mode Register 1 Format
- A/D Converter Operations
- A/D Converter Basic Operation
- Input voltage and conversion results
- A/D converter operating mode
- A/D Conversion by Software Start
- A/D Converter Cautions
- Analog Input Pin Disposition
- A/D Conversion End Interrupt Request Generation Timing
- CHAPTER 16 D/A CONVERTER
- D/A Converter Configuration
- D/A Converter Control Registers
- D/A Converter Operations
- D/A Converter Cautions
- CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES)
- Serial Interface Channel 0 Functions
- Serial Bus Interface (SBI) System Configuration Example
- Serial Interface Channel 0 Configuration
- Serial Interface Channel 0 Control Registers
- Timer Clock Select Register 3 Format
- Serial Operating Mode Register 0 Format
- Serial Bus Interface Control Register Format
- Interrupt Timing Specify Register Format
- Serial Interface Channel 0 Operations
- wire serial I/O mode operation
- Wire Serial I/O Mode Timings
- Circuit of Switching in Transfer Bit Order
- SBI mode operation
- SBI Transfer Timings
- Bus Release Signal
- Addresses
- Commands
- Acknowledge Signal
- RELT, CMDT, RELD, and CMDD Operations (Master)
- ACKT Operation
- ACKE Operations
- ACKD Operations
- Various Signals in SBI Mode
- Pin Configuration
- Address Transmission from Master Device to Slave Device (WUP = 1)
- Command Transmission from Master Device to Slave Device
- Data Transmission from Master Device to Slave Device
- Data Transmission from Slave Device to Master Device
- Serial Bus Configuration Example Using 2-Wire Serial I/O Mode
- RELT and CMDT Operations
- SCK0/P27 pin output manipulation
- CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries)
- Serial Interface Channel 0 Block Diagram
- Serial Interface Channel 0 Interrupt Request Signal Generation
- Operation stop mode
- I 2 C bus mode operation
- I 2 C Bus Serial Data Transfer Timing
- Start Condition
- Stop Condition
- Wait Signal
- Start Condition Output
- Slave Wait Release (Transmission)
- Slave Wait Release (Reception)
- Restrictions in I 2 C bus mode
- SCK0/SCL/P27 pin output manipulation
- SCK0/SCL/P27 Pin Configuration
- CHAPTER 19 SERIAL INTERFACE CHANNEL 1
- Serial Interface Channel 1 Configuration
- Serial Interface Channel 1 Control Registers
- Serial Operation Mode Register 1 Format
- Automatic Data Transmit/Receive Control Register Format
- Automatic Data Transmit/Receive Interval Specify Register Format
- Serial Interface Channel 1 Operations
- wire serial I/O mode operation with automatic transmit/receive function
- Basic Transmission/Reception Mode Operation Timings
- Basic Transmission/Reception Mode Flowchart
- Basic Transmission Mode Operation Timings
- Basic Transmission Mode Flowchart
- Buffer RAM Operation in 6-byte Transmission (in Basic Transmit Mode)
- Repeat Transmission Mode Operation Timing
- Repeat Transmission Mode Flowchart
- Buffer RAM Operation in 6-byte Transmission (in Repeat Transmit mode)
- Automatic Transmission/Reception Suspension and Restart
- System Configuration when the Busy Control Option is Used
- Operation Timings when Using Busy Control Option (BUSY0 = 0)
- Busy Signal and Wait Cancel (BUSY0 = 0)
- Operation Timings when Using Busy & Strobe Control Option (BUSY0 = 0)
- Automatic Data Transmit/Receive Interval
- Operation Timing with Automatic Data Transmit/Receive Function Performed by Internal Clock
- Interval Timing through CPU Processing (when the External Clock is Operating)
- CHAPTER 20 SERIAL INTERFACE CHANNEL 2
- Serial Interface Channel 2 Configuration
- Baud Rate Generator Block Diagram
- Serial Interface Channel 2 Control Registers
- Asynchronous Serial Interface Mode Register Format
- Serial Interface Channel 2 Operating Mode Settings
- Asynchronous Serial Interface Status Register Format
- Baud Rate Generator Control Register Format
- Relationship between Main System Clock and Baud Rate
- Serial Interface Channel 2 Operation
- Asynchronous serial interface (UART) mode
- Asynchronous Serial Interface Transmit/Receive Data Format
- Asynchronous Serial Interface Transmission Completion Interrupt Request Generation Timing
- Asynchronous Serial Interface Reception Completion Interrupt Request Generation Timing
- Receive Error Timing
- State of Receive Buffer Register (RXB) When Receive Operation is Stopped and Whether Interrupt Request (INTSR) is Generated or Not
- wire serial I/O mode
- Wire Serial I/O Mode Timing
- Restrictions on using UART mode
- Period that Reading Receive Buffer Register is Prohibited
- CHAPTER 21 REAL-TIME OUTPUT PORT
- Real-time Output Buffer Register Configuration
- Real-Time Output Port Control Registers
- Real-time Output Port Control Register Format
- CHAPTER 22 INTERRUPT FUNCTIONS
- Interrupt Sources and Configuration
- Basic Configuration of Interrupt Function
- Interrupt Function Control Registers
- Interrupt Request Flag Register Format
- Interrupt Mask Flag Register Format
- Priority Specify Flag Register Format
- Noise Eliminator Input/Output Timing (during Rising Edge Detection)
- Program Status Word Format
- Interrupt Servicing Operations
- Flowchart from Non-Maskable Interrupt Generation to Acknowledge
- Non-Maskable Interrupt Request Acknowledge Operation
- Maskable interrupt request acknowledge operation
- Interrupt Request Acknowledge Processing Algorithm
- Software interrupt request acknowledge operation
- Multiple interrupt servicing
- Multiple Interrupt Example
- Interrupt request reserve
- Test Functions
- Format of Interrupt Request Flag Register 1L
- Test input signal acknowledge operation
- CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION
- Pin Functions in Separate Bus Mode
- Memory Map when Using External Device Expansion Function
- External Device Expansion Function Control Register
- Internal Memory Size Switching Register Format
- External Bus Type Select Register Format
- External Device Expansion Function Timing
- Instruction Fetch from External Memory in Multiplexed Bus Mode
- External Memory Read Timing in Multiplexed Bus Mode
- External Memory Write Timing in Multiplexed Bus Mode
- External Memory Read Modify Write Timing in Multiplexed Bus Mode
- Timings in separate bus mode
- Instruction Fetch from External Memory in Separate Bus Mode
- External Memory Read Timing in Separate Bus Mode
- External Memory Write Timing in Separate Bus Mode
- External Memory Read Modify Write Timing in Separate Bus Mode
- CHAPTER 24 STANDBY FUNCTION
- Standby function control register
- Standby Function Operations
- HALT Mode Released by Interrupt Request Generation
- HALT Mode Released by RESET Input
- STOP mode
- STOP Mode Released by Interrupt Request Generation
- STOP Mode Released by RESET Input
- CHAPTER 25 RESET FUNCTION
- Timing of Reset by RESET Input
- Hardware Status after Reset
- CHAPTER 26 ROM CORRECTION
- Correction Address Registers 0 and 1 Format
- ROM Correction Control Registers
- ROM Correction Application
- Initialization Routine
- ROM Correction Operation
- ROM Correction Example
- Program Execution Flow
- Program Transition Diagram (when Two Places are Corrected)
- Cautions on ROM Correction
- CHAPTER 27 PD78P078, 78P078Y
- Internal Memory Size Switching Register
- Internal Extension RAM Size Switching Register
- PROM Programming
- PROM write procedure
- Page Program Mode Timing
- Byte Program Mode Flowchart
- Byte Program Mode Timing
- PROM reading procedure
- Erasure Procedure ( PD78P078KL-T and 78P078YKL-T Only)
- CHAPTER 28 INSTRUCTION SET
- Legends Used in Operation List
- Description of "operation" column
- Operation List
- Instructions Listed by Addressing Type
- APPENDIX A DIFFERENCES BETWEEN PD78078, 78075B SUBSERIES, AND PD78070A
- APPENDIX B DEVELOPMENT TOOLS
- B-1 Development Tool Configuration
- B.1 Language Processing Software
- B.2 PROM Writing Tools
- B.3 Debugging Tools
- B.3.2 Software
- B.5 System Upgrading from Former-type In-circuit Emulator for 78K/0 Series to IE-78001-R-A
- B-2 TGC-100SDW Drawing (For Reference Only)
- B-3 EV-9200GF-100 Drawing (For Reference Only)
- B-4 EV-9200GF-100 Recommended Footprints (For Reference Only)
- APPENDIX C EMBEDDED SOFTWARE
- APPENDIX D REGISTER INDEX
- D.2 Register Symbol Index
- APPENDIX E REVISION HISTORY
manualsdatabase
Your AI-powered manual search engine